PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 105

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

7
7.1
PCI
mechanism for operating systems to control add-in
boards for power management. It defines four PCI
functional power states—D
D
optional. State D
consumption and state D
• D
• D
• D
• D
• D
• D
From a power management perspective, the PCI Bus
can be characterized at any point in time by one of
four power management states—B
• B
• B
PCI 9030 Data Book Version 1.4
© 2002 PLX Technology, Inc. All rights reserved.
0
On Reset or from state D
only PCI Target transactions.
state D
PCI 9030.
Supports PCI Configuration cycles to function if
clock is running. Supports Wake-up Event from
function, but not standard PCI interrupts. When
programmed for state D
occurs. The PCI Bus drivers must be disabled.
PME# context must be retained during this
soft reset.
All context is lost in this state.
and clock frequency, PCI r2.2 compliant. Fully
operational bus activity. This is the only Power
Management state in which data transactions
can occur.
power with clock frequency, PCI r2.2 compliant.
PME Event driven bus activity. V
devices on the bus, and no transactions are allowed
to occur on the bus.
Supports PCI Configuration cycles to function
if clock is running (Memory, I/O, Bus Mastering,
and Interrupts are disabled). It also supports the
Wake-up Event from function, but not standard
PCI interrupts. Not supported by the PCI 9030.
and D
0
0
1
2
3hot
3cold
0
1
—Uses less power than State D
—Uses very little power.
—Intermediate power management state. Full
(Uninitialized)—Enters this state from Power-
(Active)—All functions active.
(Fully On)—Bus is fully usable with full power
Power
—Uses lower power than any other state.
PCI POWER MANAGEMENT
OVERVIEW
—No power. Supports only Bus reset.
2
3
. Light Sleep State. Not supported by the
are required, while states D
Mgmt.
0
represents the highest power
r1.1
3
the least.
0
, an internal soft reset
0
3hot
, D
provides
1
or D
, D
0
CC
, B
2
3cold
0
, and D
, and more than
is applied to all
1
, B
. Supports
1
a
2
and D
, and B
3
standard
. States
2
3
are
:
• B
• B
All system PCI Buses have an originating device,
which can support one or more power states. In most
cases, this creates a bridge (such as, a Host-to-PCI
Bus or a PCI-to-PCI bridge).
Function States must be at the same or lower energy
state than the bus on which they reside.
7.2
The PCI 9030 passes power management information
and has no inherent power-saving feature. The
PCI 9030 supports D
PCI 9030 does not support PME# assertion in the
D
The PCI Status register (PCISR) and the New
Capability
whether a new capability (the Power Management
function) is available. The New Capability Functions
Support bit (PCISR[4]) enables a PCI BIOS to identify
a New Capability function support. This bit is
executable for writes from the serial EEPROM and
reads from the PCI Bus. CAP_PTR provides an offset
into PCI Configuration Space, the start location of the
first item in a New Capabilities Linked List.
The Power Management Capability ID register
(PMCAPID)
Capability ID, 01h, assigned by the PCI SIG. The
Power Management Next Capability Pointer register
(PMNEXT) points to the first location of the next item
in the capabilities linked list. If Power Management is
the last item in the list, then this register should be set
to 0h. The default value for the PCI 9030 is 48h
(Hot Swap).
For the PCI 9030 to change the power state and
assert PME#, the serial EEPROM or PCI Host should
set the PME_En bit (PMCSR[8]=1). The Local Host
then determines to which power state the backplane
3cold
power clock frequency stopped, PCI r2.2 compliant
(in the low state). PME Event-driven bus activity.
V
the clock is stopped and held in the Low state.
Event-driven bus activity. V
all devices on the PCI Bus.
CC
2
3
—Intermediate power management state. Full
(Off)—Power to the bus is switched off. PME
state).
is applied to all devices on the bus; however,
PCI POWER MANAGEMENT
FUNCTIONAL DESCRIPTION
Pointer
specifies
0
register
, D
the
3hot
, and D
CC
Power
(CAP_PTR)
is removed from
3cold
Management
states (the
indicate
7-1