PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 148

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

Section 10
Registers
Register 10-59. (CNTRL; 50h) PCI Target Response, Serial EEPROM, and Initialization Control
10-34
11:10
13:12
Bit
5:0
14
15
6
7
8
9
Reserved.
PCI Target Write FIFO Full Condition. Value of 1 guarantees that when the
PCI Target Write FIFO is full with PCI Target Write data, there is always one
location remaining empty for the PCI Target Read address to be accepted
by the PCI 9030. Value of 0 Retries all PCI Target Read accesses when the
PCI Target Write FIFO is full with PCI Target Write data.
Local Arbiter LGNT Signal Select Enable. Value of 1 selects LGNT to
remain active until LREQ is de-asserted, although the PCI 9030 has a
PCI Target transaction pending. Value of 0 selects LGNT to be de-asserted
as soon as the PCI 9030 detects a PCI Target transaction pending and waits
for LREQ to be de-asserted (Preempt condition).
READY# Timeout Enable. Value of 1 enables READY# timeout enable.
READY# Timeout Select. Values:
1 = 64 clocks
0 = 32 clocks
PCI Target Delayed Write Mode. Delay in LCLKs of ADS# from valid address.
Values:
00 = 0 LCLKs
01 = 4 LCLKs
PCI Configuration Base Address Register (PCIBAR) Enables. Values:
00, 11 = PCIBAR0 (Memory) and PCIBAR1 (I/O) enabled
01
10
Note: PCIBAR0 and PCIBAR1 should be enabled for the PC platform.
PCI r2.2 Features Enable. When set to 1, the PCI 9030 performs all PCI Read
and Write transactions in compliance with PCI r2.2. Setting this bit enables
Delayed Reads, 2
rules, and enables the option to select PCI Read No Write Mode (Retries for
writes) (bit [17]) and/or PCI Read with Write Flush Mode (bit [15]). Refer to
Section 4.2.1.2 for additional information.
Value of 0 causes TRDY# to remain de-asserted on reads until Read data
is available. If Read data is not available before the PCI Target Retry Delay
Clocks counter (bits [22:19]) expires, a PCI Retry is issued.
PCI Read with Write Flush Mode. When the PCI r2.2 Features Enable bit
is set (bit [14]=1), value of 1 flushes a pending Delayed Read cycle if a Write
cycle is detected. Value of 0 (or bit [14]=0) does not affect a pending Delayed
Read when a Write cycle occurs.
= PCIBAR0 (Memory) only
= PCIBAR1 (I/O) only
15
PCI Clock timeout on Retries, 16- and 8-clock PCI latency
10 = 8 LCLKs
11 = 16 LCLKs
Description
© 2002 PLX Technology, Inc. All rights reserved.
Read
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
PCI 9030 Data Book Version 1.4
Write
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Control Registers
Value after
Reset
0h
00
00
0
0
0
0
0
0