PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 159

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

Pinout Common to All Bus Modes
Table 11-9. PCI System Bus Interface Pins
PCI 9030 Data Book Version 1.4
© 2002 PLX Technology, Inc. All rights reserved.
AD[31:0]
C/BE[3:0]#
DEVSEL#
ENUM#
FRAME#
IDSEL
INTA#
IRDY#
LOCK#
Symbol
Signal Name
Address
and Data
Bus
Command
and Byte
Enables
Device
Select
Enumeration
Cycle Frame
Initialization
Device
Select
Interrupt A
Initiator
Ready
Lock
Total
Pins
32
4
1
1
1
1
1
1
1
Type
STS
Pin
PCI
PCI
PCI
PCI
OD
OD
I/O
TS
O
O
O
I
I
I
I
I
CompactPCI
Bias Voltage
Precharge
Hot Swap
V
V
1V
1V
1V
1V
1V
1V
1V
I/O
I/O
173-175, 2-6,
41-43, 46-50
7, 19, 29, 40
9-12, 15-18,
PQFP Pin
30, 33-39,
Number
170
23
51
20
21
25
8
M1, L4, M2,
M3, N3, P2,
A3, D4, B3,
C3, C2, B1,
C1, D3, E4,
D1, E3, E2,
K2, K3, K1,
D2, G5, J4,
F3, F2, F4,
K4, L2, L3,
µBGA Pin
F1, J2, J1,
Number
P3, M4
G1
N4
G2
E5
B4
G3
H2
L1
All multiplexed on the same PCI
pins. The Bus transaction consists
of an Address phase, followed by
one or more Data phases. The
PCI 9030 supports both Read and
Write bursts.
All multiplexed on the same PCI
pins. During the Transaction
Address phase, defines the bus
command. During the Data phase,
used as byte enables. Refer to the
PCI r2.2 for further details.
When actively driven, indicates the
driving device decoded its address
as Target of current access.
Interrupt output set when an
adapter using the PCI 9030 was
recently inserted or ready to be
removed from a PCI slot. Used
for implementing CompactPCI
Hot Swap.
Driven by the current Master to
indicate the beginning and duration
of an access. FRAME# is asserted
to indicate the bus transaction
is beginning. While FRAME# is
asserted, Data transfers continue.
When FRAME# is de-asserted,
the transaction is in the final
Data phase.
Used as a chip select during
Configuration Read and Write
transactions.
PCI Interrupt request.
Indicates initiating agent (Bus
Master) ability to complete the
current transaction Data phase.
Indicates an atomic operation that
may require multiple transactions
to complete.
Function
Pin Description
Section 11
11-7