PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 141

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

Local Configuration Registers
Register 10-51. (LAS3BRD; 34h) Local Address Space 3 Bus Region Descriptor
PCI 9030 Data Book Version 1.4
© 2002 PLX Technology, Inc. All rights reserved.
12:11
14:13
19:15
21:20
23:22
10:6
Bit
4:3
0
1
2
5
Local Address Space 3 Burst Enable. Writing 1 enables bursting. Writing 0
disables bursting. If burst is disabled, the Local Bus performs continuous
single cycles for Burst PCI Read/Write cycles. PCI reads are completed as
single cycle on the PCI Bus if Local burst is disabled or prefetch is disabled
(bits [5:3]=100).
Local Address Space 3 READY# Input Enable. Writing 1 enables READY#
input. Writing 0 disables READY# input.
Local Address Space 3 BTERM# Input Enable. Writing 1 enables BTERM#
input. Writing 0 disables BTERM# input. For more information, refer to
Section 2.2.4.3.
Prefetch Count. Number of Lwords to prefetch during Memory Read cycle.
Used only if bit 5 is high (Prefetch Counter enabled). Values:
00 = Do not prefetch. Only read bytes specified by C/BE lines.
01 = Prefetch four Lwords if bit 5 is set.
10 = Prefetch eight Lwords if bit 5 is set.
11 = Prefetch 16 Lwords if bit 5 is set.
Prefetch Counter Enable. When set to 1 and the Prefetch Count is not 00, the
PCI 9030 prefetches up to the number of Lwords specified in the Prefetch
Count. When set to 0, the PCI 9030 ignores the count and continues
prefetching, until terminated by PCI Bus transaction completion if Read Ahead
mode is disabled (CNTRL[16]=0), or if Read Ahead mode is enabled, until the
Read FIFO fills. To disable prefetch, enable the Prefetch Counter and set the
prefetch count to 0 (bits [5:3]=100).
NRAD Wait States. Number of Read Address-to-Data wait states (0-31).
(Wait states between the Address cycle and first Read Data cycle.)
NRDD Wait States. Number of Read Data-to-Data wait states (0-3).
(Wait states between consecutive Data cycles of a Burst read.)
NXDA Wait States. Number of Read/Write Data-to-Address wait states (0-3).
LAD/LD Bus Write data is not valid during NXDA wait states. (Wait states
between consecutive bus requests. NXDA wait states are inserted only after
the last Data transfer of a PCI Target access.)
NWAD Wait States. Number of Write Address-to-Data wait states (0-31).
LAD/LD Bus data is valid during NWAD wait states. (Wait states between
the Address cycle and first Write Data cycle.)
NWDD Wait States. Number of Write Data-to-Data wait states (0-3).
(Wait states between consecutive Data cycles of a Burst write.)
Local Address Space 3 Local Bus Width. Writing of the following values
indicates the associated bus width:
00 = 8-bit
01 = 16-bit
10 = 32-bit
11 = Reserved
Description
Read
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Write
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Value after
Section 10
Reset
00000
00000
Registers
00
00
00
00
10
0
0
0
0
10-27