PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 161

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

Pinout Common to All Bus Modes
Table 11-10. Local Bus Mode Independent Interface Pins
PCI 9030 Data Book Version 1.4
© 2002 PLX Technology, Inc. All rights reserved.
BCLKo
CPCISW
CS[1:0]#
GPIO0
WAITo#
GPIO1
LLOCKo#
GPIO2
CS2#
GPIO3
CS3#
Symbol
Buffered Clock
Out
CompactPCI
Switch
Chip Selects
General
Purpose I/O 0
WAIT Out
General
Purpose I/O 1
LLOCK Out
General
Purpose I/O 2
Chip Select 2
Out
General
Purpose I/O 3
Chip Select 3
Out
Signal Name
Total
Pins
1
1
2
1
1
1
1
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
Type
Pin
TP
TS
I/O
TS
I/O
TS
I/O
TS
I/O
TS
O
O
I
PQFP Pin
148, 147
Number
154
155
156
157
71
54
µBGA Pin
Number
B9, C9
K8
P4
D8
A8
D7
B7
Provides a buffered version PCI clock for
optional use by the Local Bus. Not in phase
with the PCI clock.
CompactPCI board latch status input.
General purpose chip selects. The base and
range of each is programmable by Configuration
registers.
Can be programmed to a configurable general
purpose I/O pin, GPIO0, or Local Bus WAIT out
pin, WAITo#. WAITo# is asserted when wait
states are caused by the internal wait state
generator. Serves as an output to provide
ready-out status.
Default functionality is GPIO0 input.
Pin configuration occurs when the serial
EEPROM contents are loaded following
PCI reset, or upon subsequent writing to
the GPIOC[1:0] register bits.
Can be programmed to a configurable general
purpose I/O pin, GPIO1, or Local Bus LLOCK
out pin, LLOCKo#. LLOCKo# indicates an
atomic operation that may require multiple
transactions to complete and can be used
by the Local Bus to lock resources.
Default functionality is GPIO1 input.
Pin configuration occurs when the serial
EEPROM contents are loaded following
PCI reset, or upon subsequent writing to
the GPIOC[4:3] register bits.
The PCI 9030 asserts LLOCKo# during the first
clock of an atomic operation (Address cycle),
and de-asserts it a minimum of one clock
following the last Bus access for the atomic
operation. LLOCKo# is de-asserted after
the PCI 9030 detects PCI FRAME#, with
PCI LOCK# concurrently de-asserted.
Can be programmed to a configurable general
purpose I/O pin, GPIO2, or as Chip Select 2
output pin, CS2#.
Default functionality is GPIO2 input.
Pin configuration occurs when the serial
EEPROM contents are loaded following
PCI reset, or upon subsequent writing to
the GPIOC[7:6] register bits.
Can be programmed to a configurable general
purpose I/O pin, GPIO3, or as Chip Select 3
output pin, CS3#.
Default functionality is GPIO3 input.
Pin configuration occurs when the serial
EEPROM contents are loaded following
PCI reset, or upon subsequent writing to
the GPIOC[10:9] register bits.
Function
Pin Description
Section 11
11-9