PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 55

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

Direct Data Transfer Mode
4.2.1.8.3
A
encompassing Local Bus Addresses 01200000h
through 012FFFFFh is to be configured for Local
Address Space 0. Assume the BIOS System
Resource Manager allocates 1 MB with a PCI Base
Address of 34500000h. The Local memory is then
accessible at PCI Addresses 34500000h through
345FFFFFh.
a. Program the serial EEPROM as follows:
b. PCI Initialization software writes all ones (1) to the
4.2.1.8.4
During a PCI Target transfer, each of five spaces—
Spaces 0, 1, 2, and 3, and Expansion ROM—can be
programmed to operate in an 8-, 16-, or 32-bit Local
Bus width by encoding the Local Byte Enables
(LBE[3:0]#). LBE[3:0]# (PQFP—pins 55, 58-60,
respectively;
respectively) are encoded, based on the configured
bus width, as follows.
32-Bit Bus—The four byte enables indicate which of
the four bytes are active during a Data cycle:
• LBE3# Byte Enable 3—LAD[31:24]
• LBE2# Byte Enable 2—LAD[23:16]
• LBE1# Byte Enable 1—LAD[15:8]
• LBE0# Byte Enable 0—LAD[7:0]
PCI 9030 Data Book Version 1.4
© 2002 PLX Technology, Inc. All rights reserved.
• Range—FFF00008h [1 MB, decode the upper
• Local Base Address (Remap)—01200001h
PCI Base Address register, then reads it back.
• The PCI 9030 returns a value of FFF00008h,
• PCI Base Address—34500008h (PCI Base
1 MB
12 PCI Address bits, and set the Prefetchable
bit (LAS0RR[3]=1)].
(Local Base Address for PCI-to-Local
accesses). Bit 0 must be set to enable address
decoding (LAS0BA[0]=1).
after which the PCI software writes the base
address it assigned into the PCI Base Address
register(s).
Address for Access to Local Address Space 0
register, PCIBAR2). The PCI Base Address is
always aligned on a boundary determined by
address space size. The Prefetchable bit is set
(PCIBAR2[3]=1).
prefetchable
PCI Target Example
PCI Target Byte Enables
(Multiplexed Mode)
µ
BGA—pins
Local
M5,
Address
P5,
M6,
Space
N6,
16-Bit Bus—LBE[3, 1:0]# are encoded to provide
BHE#, LAD1, and BLE#, respectively:
• LBE3# Byte High Enable (BHE#)—LAD[15:8]
• LBE2# not used
• LBE1# Address bit 1 (LAD1)
• LBE0# Byte Low Enable (BLE#)—LAD[7:0]
8-Bit Bus—LBE[1:0]# are encoded to provide
LAD[1:0], respectively:
• LBE3# not used
• LBE2# not used
• LBE1# Address bit 1 (LAD1)
• LBE0# Address bit 0 (LAD0)
During the Address phase, LAD[1:0] are valid address
bits with the same value as LBE[1:0]#.
4.2.1.8.5
During a PCI Target transfer, each of five spaces—
Spaces 0, 1, 2, and 3, and Expansion ROM—can be
programmed to operate in an 8-, 16-, or 32-bit Local
Bus width by encoding the Local Byte Enables
(LBE[3:0]#). LBE[3:0]# (PQFP—pins 55, 58-60,
respectively;
respectively) are encoded, based on the configured
bus width, as follows.
32-Bit Bus—The four byte enables indicate which of
the four bytes are active during a Data cycle:
• LBE3# Byte Enable 3—LD[31:24]
• LBE2# Byte Enable 2—LD[23:16]
• LBE1# Byte Enable 1—LD[15:8]
• LBE0# Byte Enable 0—LD[7:0]
16-Bit Bus—LBE[3, 1:0]# are encoded to provide
BHE#, LA1, and BLE#, respectively:
• LBE3# Byte High Enable (BHE#)—LD[15:8]
• LBE2# not used
• LBE1# Address bit 1 (LA1)
• LBE0# Byte Low Enable (BLE#)—LD[7:0]
8-Bit Bus—LBE[1:0]# are encoded to provide LA[1:0],
respectively:
• LBE3# not used
• LBE2# not used
• LBE1# Address bit 1 (LA1)
• LBE0# Address bit 0 (LA0)
PCI Target Byte Enables
(Non-Multiplexed Mode)
µ
BGA—pins
PCI Target (Direct Slave) Operation
M5,
P5,
M6,
Section 4
N6,
4-7