PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 193

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

PCI Target
PCIBAR0 3-7, 4-4, 10-7
PCIBAR1 3-7, 4-4, 10-7
PCIBAR2 4-4, 10-8
PCIBAR3 4-4, 10-8
PCIBAR4 4-4, 10-9
PCIBAR5 4-4, 10-9
PCIBISTR (not supported) 10-6
PCICCR 3-3, 10-5
PCICIS (not supported) 10-10
PCICLSR 3-6, 10-6
PCICR 6-2, 10-4
PCIERBAR 3-7, 4-4, 10-10
PCIHTR 3-6, 10-6
PCIIDR 3-3, 10-4
PCIILR 3-3, 10-11
PCIIPR 3-3, 10-11
PCILTR (not supported) 10-6
PCIMGR (not supported) 10-11
PCIMLR (not supported) 10-11
PCIREV 3-3, 10-5
PCISID 3-3, 10-10
PCISR 3-3, 7-1, 10-5
PCISVID 3-3, 10-4, 10-10
PCLK 11-8, 12-2, 13-3, 13-6
performance features 1-3
PERR# 11-8, 13-3, 13-6
PCI 9030 Data Book Version 1.4
© 2002 PLX Technology, Inc. All rights reserved.
4-1–4-45
Abort 2-1, 10-5
accesses 10-19, 10-20
Big Endian/Little Endian cycle reference table 2-11
BTERM# input 2-9
bursting 1-3
command codes 2-1
Delayed Read mode 1-5, 4-2, 10-34
Delayed Write mode 1-3, 1-5, 10-34
description 1-1
FIFO depth 1-3, 1-5
interface chip 1-3
power management 7-1
Power mode example 7-3
Read Ahead mode 1-1, 1-3, 2-10, 3-1, 10-35
READY# Timeout, Local Bus 1-5, 10-34
response (CNTRL) 10-3, 10-34–10-35
SMARTarget 1-1
timing diagram 4-16
transactions 1-3
wait states 2-8
8- or 16-bit Local Bus, to 2-2
Big Endian/Little Endian mode, Local Bus 2-10
partial Lword 2-10
timing diagram 5-4
physical specs 13-1–13-8
PICMG 2.1, R2.0 1-2, 1-3, 8-1, 8-1
pinout
pins
pins, Debug and Test
pins, Hot Swap
pins, Local Bus Mode Independent Interface
pins, Multiplexed Bus Mode Interface
pins, no connect (NC, µBGA)
µBGA 13-6
PQFP 13-3
BD_SEL# 8-1
CPCISW 8-1
ENUM# 1-2, 8-1
LEDon# 8-1
V
See pins, Test and Debug
BD_SEL# 11-1, 11-6
CPCISW 11-1, 11-9
ENUM# 11-2, 11-7
LEDon# 11-2, 11-10
BCLKo 11-9, 13-3, 13-6
CPCISW 11-1, 11-9, 13-3, 13-6
CS[1:0]# 11-9, 13-3, 13-6
CS2# 11-3, 11-9, 13-3, 13-6
CS3# 11-3, 11-9, 13-3, 13-6
GPIO[8, 3:0] 4-11, 6-5, 11-3, 11-10, 13-3
LCLK 11-1, 11-10, 12-2, 13-3, 13-6
LEDon# 11-2, 11-10, 13-3, 13-6
LGNT 2-5, 11-10, 13-3, 13-6
LINTi[2:1] 11-2, 11-10, 13-3, 13-6
LLOCKo# 2-4, 11-3, 11-9, 13-3, 13-6
LPMESET 11-2, 11-11, 13-3, 13-6
LPMINT# 11-11, 13-3, 13-6
LREQ 2-5, 11-2, 11-11, 13-3, 13-6
LRESETo# 3-1, 11-11, 13-3, 13-6
MODE 11-2, 11-11, 13-3, 13-6
WAITo# 2-5, 11-3, 11-9, 13-3, 13-6
ADS# 2-4, 11-12, 13-3, 13-6
ALE 2-4, 11-12, 13-3, 13-6
BLAST# 11-12, 13-3, 13-6
BTERM# 2-8, 11-1, 11-12, 13-3, 13-6
GPIO[7:4] 4-11, 6-5, 11-3, 11-13, 13-3, 13-6
LA[23:2] 11-13, 13-3, 13-6
LA[27:24] 11-3, 11-12, 13-3, 13-6
LAD[31:0] 2-3, 11-3, 11-13, 13-3, 13-6
LBE[3:0]# 2-4, 11-13, 13-3, 13-6
LW/R# 2-4, 11-14, 13-3, 13-6
RD# 2-4, 10-22–10-30, 11-14, 13-3, 13-6
READY# 2-5, 2-8, 11-2, 11-14, 13-3, 13-6
WR# 2-5, 10-22–10-30, 11-14, 13-3, 13-6
11-4, 13-6
IO
8-1
to pins, no connect (NC, µBGA)
PCI Target
Index-7