PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 18

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

Preface
TERMS AND DEFINITIONS
• PCI Target (Direct Slave)
Data Assignment Conventions
REVISION HISTORY
xviii
1/31/2001
10/1999
10/1999
11/1999
12/1999
12/2001
01/2002
05/2002
3/1999
8/1999
4/2000
External PCI Bus Initiator initiates Data write/read to/from the Local Bus
Date
2 bytes (16 bits)
4 bytes (32 bits)
1 byte (8 bits)
Data Width
Version
0.90
0.90
0.90
0.91
0.92
0.93
1.0
1.1
1.2
1.3
1.4
New Release PCI 9030 Preliminary Data Book, Version 0.9.
Update.
Initial Release Red Book.
Update.
Update.
Initial Release Blue Book.
Production Release.
Incorporated 1/31/2001 Addendum changes, including past design notes.
Released version 1.2.
Updated Hot-Plug support from Revision 1.0 to Revision 1.1.
Updated PICMG 2.1 Hot Swap support from Revision 1.0 to Revision 2.0.
Corrected Table 2-1 for PCI Command Code response.
Renamed Section 2.2.2 from “Local Signals” to “Local Bus Signals Used in Timing Diagrams.”
Revised Section 2.2.4.2.1 Local Bus Wait State content and added Figures 2-1 and 2-2 to illustrate
wait state definitions.
Revised Sections 2.2.4.3.1 through 2.2.4.3.2.1 to clarify Local Bus bursting, Bterm mode, and BTERM# input.
Corrected LINT[1:2] polarity in Timing Diagram 4-8.
Updated Section 10 PCIBARx, EROMRR, LASxRR, EROMBRD, and LASxBRD register bit descriptions.
Replaced the PMDATASEL register description (missing in version 1.1).
Corrected LASxBRD[25] descriptions for Big Endian Byte Lane mode to indicate this bit is functional only
in Big Endian mode.
Updated the PMC register description to match PCI Power Mgmt. r1.0. (Refer to PCI 9030 Design Notes #1
for a revised PMC register description compliant with PCI Power Mgmt. r1.1).
Added pull-down recommendation to TRST# pin description and changed READY# wait state generator-
related information in Section 11.
Documented additional reset behavior in Section 11.1.
Updated ALE Timing illustration, Figure 12-3.
Figure 13-2 modified to remove non-metric measurements.
Replaced Figure 13-6, “180-Pin µBGA Package Layout—Underside View” and Table 13-3,
“180-Pin µBGA PCI 9030 Pinout” with new Figure 13-6, “180-Pin µBGA Physical Layout with Pinout.”
Updated package mechanical drawings for changed marking content, which affects inspection, pattern
recognition, and tray and board loading equipment.
Revised and clarified Figures 13-4 and 13-6.
Updated Section 10 EROMBRD[19:15] and LASxBRD[19:15] register bit descriptions, and associated text that
appears elsewhere in the data book, to include LD signal.
Corrected Section 10 EROMBRD[5] and LASxBRD[5] register bit descriptions regarding “when set to 0”.
Corrected Fiducial locations and Pad Pitch measurement in Figure 13-2. Only affected pages list the revision
and date change.
PCI 9030 Convention
Lword
Word
Byte
Comment
© 2002 PLX Technology, Inc. All rights reserved.
PCI 9030 Data Book Version 1.4