PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 39

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

3
3.1
During power-on, the PCI RST# signal resets the
default values of the PCI 9030 internal registers. In
return, the PCI 9030 outputs the local LRESETo#
signal and checks for a serial EEPROM. If a serial
EEPROM exists, and the first 33 bits are not all ones
(1), the PCI 9030 loads the internal registers from the
serial EEPROM. Otherwise, default values are used.
The PCI 9030 Configuration registers can be written
only by the optional serial EEPROM or PCI Host
processor. During serial EEPROM initialization, the
PCI 9030 response to Direct Slave accesses is
Retrys.
3.2
3.2.1
PCI Bus RST# input assertion causes all PCI Bus
outputs to float, asserts both Local reset outputs
LRESETo# and LEDon#, and floats all other Local Bus
output and I/O pins, except BCLKo, EECS, EEDI,
EESK, ENUM#, LGNT, LPMINT#, multiplexed I/O pins
LA[27:24]/GPIO[4:7], and the Local Data Bus signals.
The LA[27:24]/GPIO[4:7] multiplexed I/O pins, and the
Non-multiplexed mode LD[31:0] data or Multiplexed
mode LAD[31:0] address/data I/O pins, are driven low
during PCI reset. (Refer to PCI 9030 Errata #4.)
3.2.2
A PCI host can set the PCI Adapter Software Reset bit
(CNTRL[30]=1) to reset the PCI 9030 and assert
LRESETo#. The PCI and Local Configuration register
contents are not reset as a result. When the Software
Reset bit is set, the PCI 9030 responds only to
Configuration register accesses, and not to Local Bus
accesses. The PCI 9030 remains in this reset
condition
(CNTRL[30]=0). The PCI Interface is not reset.
Note:
(CNTRL[16]=1), disable it prior to a software reset, or if following
a software reset, perform a PCI Target read of any valid Local Bus
address, except the next sequential Lword referenced from the last
PCI Target read, to flush the PCI Target Read FIFO.
PCI 9030 Data Book Version 1.4
© 2002 PLX Technology, Inc. All rights reserved.
If PCI Target Read Ahead mode is enabled
SERIAL EEPROM RESET AND INITIALIZATION
INITIALIZATION
RESET
PCI Bus RST# Input
Software Reset
until
the
PCI
Host
clears
the
bit
3.2.3
LRESETo# is asserted when the PCI Bus RST# input
is asserted or the PCI Adapter Software Reset bit is
set (CNTRL[30]=1).
3.3
After reset, the PCI 9030 attempts to read the serial
EEPROM to determine its presence. An active start bit
set to 0 indicates a serial EEPROM is present. The
PCI 9030 supports 93CS56L (2K bit) or 93CS66L
(4K bit). (Refer to manufacturer’s data sheet for the
particular serial EEPROM being used.) The first
33 bits are then checked to verify that the serial
EEPROM is programmed. If the first 33 bits are all
ones (1), a blank serial EEPROM is present.
For blank serial EEPROM conditions, the PCI 9030
reverts to the default values. (Refer to Table 3-1.)
When the Serial EEPROM Valid bit is set to 1
(CNTRL[28]=1), if programmed, real or random data is
detected in the serial EEPROM.
An active Start bit set to 1 indicates that a serial
EEPROM is not present. For missing serial EEPROM
conditions, the PCI 9030 stops the serial EEPROM
load and reverts to the default values within 13 serial
EEPROM clocks (EESK).
The 3.3V serial EEPROM clock is derived from the
PCI clock, generated by the PCI 9030 by internally
dividing the PCI clock by 132.
The serial EEPROM can be read or written from the
PCI Bus. The Serial EEPROM Control Register bits
(CNTRL[28:24]) control the PCI 9030 pins that enable
reading or writing of serial EEPROM data bits. (Refer
to manufacturer’s data sheet for the particular serial
EEPROM being used.)
To reload serial EEPROM data into the PCI 9030
internal registers, write 1 to the Reload Configuration
Registers bit (CNTRL[29]=1).
The serial EEPROM can also be read or written, using
the VPD function. (Refer to Section 9.) The PCI 9030
loads 34 Lwords from the serial EEPROM.
SERIAL EEPROM
Local Bus Output LRESETo#
3-1