PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 160

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

Section 11
Pin Description
Table 11-9. PCI System Bus Interface Pins (Continued)
11-8
PAR
PCLK
PERR#
PME#
RST#
SERR#
STOP#
TRDY#
Total
Symbol
Parity
Clock
Parity Error
Power
Management
Event
Reset
System Error
Stop
Target
Ready
Signal Name
Total
Pins
51
1
1
1
1
1
1
1
1
Type
STS
STS
STS
PCI
PCI
PCI
PCI
PCI
PCI
Pin
OD
OD
I/O
TS
O
O
O
O
O
I
I
Bias Voltage
CompactPCI
Connection
Precharge
Hot Swap
V
V
1V
No
1V
1V
1V
1V
I/O
I/O
PQFP Pin
Number
172
169
171
28
26
27
24
22
© 2002 PLX Technology, Inc. All rights reserved.
µBGA Pin
Number
H1
A4
H3
D5
C4
H5
H4
G4
Pinout Common to All Bus Modes
Even parity across AD[31:0] and
C/BE[3:0]#. All PCI agents require
parity generation. PAR is stable
and valid one clock after the
Address phase. For Data phases,
PAR is stable and valid one clock
after either IRDY# is asserted on
a Write transaction or TRDY# is
asserted on a Read transaction.
Once PAR is valid, it remains valid
until one clock after current Data
phase completes.
Provides timing for all transactions
on the PCI Bus and is an input to
every PCI device. The PCI 9030
operates up to 33 MHz.
Note:
trace length for the PCI PCLK
signal must be 2.5 inches
±0.1 inches, and must be routed
to only one load, per PCI r2.2.
Reports data parity errors during
all PCI transactions, except during
a special cycle.
Wake-up event interrupt.
Note:
a field-effect transistor (FET)
should be used to isolate the
signal when power is removed
from the card. (Refer to PCI Power
Mgmt. r1.1.) If PME# is not used,
then connect it through a pull-up
resistor to V
Used to bring PCI-specific
registers, sequencers, and signals
to a default state.
Reports address parity errors or
any other system error where the
result is catastrophic.
Indicates the current Target is
requesting that the Master stop
the current transaction.
Indicates the Target agent
(selected device) ability to
complete the current Data phase
transaction.
PCI 9030 Data Book Version 1.4
On Expansion boards,
If PME# is implemented,
I/O
Function
.