PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 113

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

9
9.1
The PCI r2.2 Vital Product Data (VPD) function
defines a new location and access method. It also
defines the Read Only and Read/Write bits. Currently
Device ID, Vendor ID, Revision ID, Class Code,
Subsystem ID, and Subsystem Vendor ID are required
in the Configuration Space Header and for basic
device identification and configuration. Although this
information allows a device to be configured, it is not
sufficient to allow a device to be uniquely identified.
With the addition of VPD, optional information is
provided that allows a device to be uniquely identified
and tracked. These additional bits enable current and/
or future support tools and reduces the total cost of
ownership of PCs and systems.
This provides an alternate access method other than
Expansion ROM for VPD. VPD is stored in an external
serial EEPROM, which is accessed using the
Configuration Space New Capabilities function.
The
PVPDAD, and PVPDATA—are not accessible for
reads from the Local Bus. The VPD function can be
exercised only from the PCI Bus.
9.2
VPD ID. Bits [7:0] (PVPDCNTL[7:0]; PCI:4Ch).
The PCI SIG assigned these bits a value of 03h. The
VPD ID is hardwired.
Next_Cap Pointer. Bits [15:8] (PVPD_NEXT[7:0];
PCI:4Dh). These bits either point to the next
New Capability structure, or are set to 0 if this is
the last capability in the structure. The PCI 9030
defaults to 0h. This value can be overwritten from the
serial EEPROM. Bits [9:8] are reserved by PCI r2.2
and should be set to 00.
VPD Address. Bits [24:16] (PVPDAD[14:0]; PCI:4Eh).
These bits specify the Lword-aligned VPD byte
address to be accessed. All accesses are 32-bit wide;
bits [17:16] must be 00, with the maximum serial
EEPROM size being 4K bits. Bits [30:25] are ignored.
PCI 9030 Data Book Version 1.4
© 2002 PLX Technology, Inc. All rights reserved.
VPD
PCI VITAL PRODUCT DATA (VPD)
OVERVIEW
VPD CAPABILITIES REGISTER
registers—PVPDCNTL,
PVPD_NEXT,
F. Bit 31 (PVPDAD[15]; PCI:4Eh). This bit sets a flag
to indicate when a serial EEPROM data operation
completes. For Write cycles, the four bytes of data are
first written into the VPD Data bits, after which the
VPD Address is written at the same time the F flag is
set to 1. The F flag clears when the serial EEPROM
Data transfer completes. For Read cycles, the VPD
Address is written at the same time the F flag is
cleared to 0. The F flag is set when four bytes of data
are read from the serial EEPROM. (Refer to PCI 9030
Errata #1.)
VPD Data. Bits [31:0] (PVPDATA[31:0]; PCI:50h). The
PVPDATA register is not a pure read/write register.
The data read from the register depends upon the last
Read operation performed in PVPDAD[15]. VPD data
is written or read through this register. Least-
significant byte corresponding to VPD Byte at the
address specified by the VPD Address register. Four
bytes are always transferred between the register and
the serial EEPROM.
Figure 9-1. VPD Capabilities
9.3
To support VPD, the serial EEPROM is partitioned into
read-only and read/write sections.
9.4
The first 1088 bits (136 bytes) of the serial EEPROM
contain read-only information. The read-only portion of
the serial EEPROM is loaded into the PCI 9030, using
a sequential read protocol to the serial EEPROM and
occurs after PCI reset. Sequential words are read by
holding EECS asserted, following issuance of a serial
EEPROM Read command.
31
F
30
VPD Address
VPD SERIAL EEPROM
PARTITIONING
SEQUENTIAL READ ONLY
16
15
VPD Data
Pointer (0h)
Next_Cap
8
7
VPD ID
(03h)
0
9-1