PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 165

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

Multiplexed Local Bus Mode Pinout
Table 11-11. Multiplexed Bus Mode Interface Pins (Continued)
PCI 9030 Data Book Version 1.4
© 2002 PLX Technology, Inc. All rights reserved.
GPIO7
LA24
LA[23:2]
LAD[31:0]
LBE[3:0]#
Symbol
General
Purpose I/O 7
Address Bus
Address Bus
Address/
Data Bus
Byte Enables
Signal Name
Total
Pins
22
32
1
4
12 mA
12 mA
12 mA
12 mA
12 mA
Type
Pin
I/O
TS
TS
TS
I/O
TS
TS
O
O
O
PQFP Pin
72-74, 77,
55, 58-60
131-127,
125-123,
121-118,
116-114,
Number
102, 104
111-105
61-65,
67-69,
79-84,
86-87,
89-93,
95-99,
134
M12, M13, N14,
G14, G10, G12,
M7, P7, L8, N8,
N11, M11, P11,
M5, P5, M6, N6
C13, D11, C14,
D14, D12, E11,
H14, H11, H12,
L6, P6, K7, N7,
P8, L9, N9, P9,
M10, P10, L10,
M14, L13, K10,
E14, E12, F14,
L11, N12, N13,
K11, L14, K12,
F10, F12, F13,
µBGA Pin
H13, H10,
K14, J13
Number
J14, J11
C12
Can be programmed to a configurable general
purpose I/O pin, GPIO7, or as Address Bus
output pin, LA24.
Default functionality is LA24. Pin configuration
occurs when the serial EEPROM contents are
loaded following PCI reset, or upon subsequent
writing to the GPIOC[22:21] register bits.
Carries the upper 22 bits of the 28-bit physical
Address Bus. Increments during bursts indicate
successive Data cycles.
During an Address phase, the bus carries the
upper 26 bits of 28-bit physical Address Bus
[27:2]. During the Data phase, the Bus carries
32-, 16-, or 8-bit data quantities, depending on
bus width configuration:
•
•
•
During an ADS# assertion, carries the Local
Address Bus (LA[27:2]).
Encoded, based on the bus-width configuration:
32-Bit Bus
Four byte enables indicate which of the four bytes
are active during a data cycle:
•
•
•
•
16-Bit Bus
LBE[3, 1:0]# are encoded to provide BHE#, LA1,
and BLE#, respectively:
•
•
•
•
8-Bit Bus
LBE[1:0]# are encoded to provide LA[1:0],
respectively:
•
•
•
•
8-bit = LAD[7:0]
16-bit = LAD[15:0]
32-bit = LAD[31:0]
LBE3# Byte Enable 3 = LAD[31:24]
LBE2# Byte Enable 2 = LAD[23:16]
LBE1# Byte Enable 1 = LAD[15:8]
LBE0# Byte Enable 0 = LAD[7:0]
LBE3# Byte High Enable (BHE#) = LAD[15:8]
LBE2# Unused
LBE1# Address bit 1 (LA1)
LBE0# Byte Low Enable (BLE#) = LAD[7:0]
LBE3# Unused
LBE2# Unused
LBE1# Address bit 1 (LA1)
LBE0# Address bit 0 (LA0)
Function
Pin Description
Section 11
11-13