PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 31

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

Local Bus
Table 2-3. READY# Data Transfers
2.2.3.3.6
The READY# input pin has a corresponding Enable bit
in the Bus Region Descriptor register(s) (LASxBRD[1]
and/or EROMBRD[1]). If READY# is enabled, this
indicates that Write data is being accepted or Read
data is being provided by the Bus Slave. If a Bus Slave
needs to insert wait states, it can de-assert READY#
until it is ready to accept or provide data. If READY# is
disabled, then the Local Bus transfer length can be
determined by internal wait state generators. (Refer to
Table 2-3.)
2.2.3.3.7
WAITo# is an output that provides status of the
internal wait state generators. It is asserted while
internal wait states are being inserted. READY# input
is not sampled until WAITo# is de-asserted.
2.2.3.3.8
WR# is a general purpose write output strobe. The
timing is controlled by the current Bus Region
Descriptor register. The WR# strobe is asserted during
the entire data transfer.
WR# is normally asserted during address-to-data wait
states (NWAD), unless Write Strobe Delay clocks are
programmed in the Bus Region Descriptor register(s)
(LASxBRD[29:28] and/or EROMBRD[29:28]). WR#
remains asserted throughout Burst and data-to-data
wait states (NWDD). The LAD/LD Data Bus valid time
can be extended beyond WR# de-assertion if Write
Cycle Hold clocks are programmed in the Bus Region
Descriptor
EROMBRD[31:30]).
PCI 9030 Data Book Version 1.4
© 2002 PLX Technology, Inc. All rights reserved.
Device
Address
Spaces
Slave
register(s)
READY#
WAITo#
WR#
Input Enable
0
1
READY#
(LASxBRD[31:30]
Sampled
Signal
Ignored
READY# is not sampled by the PCI 9030. Data transfers determined by the internal
wait state generator. READY# is ignored and the Data transfer takes place after the
internal wait state counter expires.
READY# is sampled by the PCI 9030. Data transfers are determined by an external
device, which asserts READY# to indicate a Data transfer is taking place.
and/or
2.2.3.4
The PCI 9030 is the Local Bus Master. When the PCI
Bus initiates a new transfer request, the PCI 9030
takes Local Bus control. Another device can gain
Local Bus control by asserting LREQ. If the PCI 9030
has no cycles to run, it asserts LGNT, transferring
control to the external Master.
If the PCI 9030 requires the Local Bus for a pending
PCI Target transaction before the external Master
completes, and the PCI 9030 Local Bus Arbiter
is configured to give priority to PCI Target accesses
over external master ownership of the Local Bus
(CNTRL[7]=0), the Local Bus Arbiter de-asserts LGNT
regardless of LREQ pin state (default preempt
condition). If instead, priority is given to the external
Master (CNTRL[7]=1),
continues to assert LGNT output until the Local Bus
Master releases the bus by de-asserting LREQ.
LREQ can be pulled low or grounded to provide
permanent Local Bus ownership to the PCI 9030.
2.2.3.4.1
LGNT is asserted by the PCI 9030 to grant Local Bus
control to a Local Bus Master. When the PCI 9030
requires the Local Bus, it can signal a preempt by
de-asserting LGNT, if configured to do so in the Local
Arbiter LGNT Signal Select Enable bit (CNTRL[7]=0).
2.2.3.4.2
LREQ is asserted by a Local Bus Master to request
Local Bus use. The PCI 9030 can be made master of
the Local Bus by pulling LREQ low (or by grounding
LREQ).
Local Bus Arbitration
LGNT
LREQ
Description
the Local Bus Arbiter
PCI and Local Bus
Section 2
2-5