PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 191

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

LD[31:0]
LEDon# 8-1, 11-2, 11-10, 13-3, 13-6
Level-Sensitive mode 6-1, 6-2, 11-10
LGNT 2-5, 11-10, 13-3, 13-6
LINTi[2:1] 11-2, 11-10, 13-3, 13-6
Little Endian
LLOCKo# 1-5, 2-4, 4-44, 6-3, 10-36, 11-3, 11-9, 13-3,
local
Local Address
Local Bus 2-2–2-12
PCI 9030 Data Book Version 1.4
© 2002 PLX Technology, Inc. All rights reserved.
2-4, 11-3, 11-16, 13-3, 13-6
See Endian, Big/Little
clocks 1-4, 6-2, 11-1, 12-3–12-5
configuration registers 10-3, 10-16–10-30, 10-33
input setup 12-3
power management enumerator set 6-2
signals 2-3, 12-4
Big/Little Endian mode 2-10
bits LA[1:0] 2-2
expansion ROM local base address register 10-20
increment 11-13, 11-16
mapping 4-4
PCI 1-3, 4-7
space bus region descriptor registers 10-21–10-27
space local base address registers 10-19–10-20
space range registers 10-16–10-17
spaces 1-5, 4-1, 10-2, 10-3
characteristics 4-5
configuration registers 10-3
control 4-4
Delayed Read mode, PCI Target 4-2
FIFO, response to full or empty 4-8
I/Os 8-2
independent interface pins 11-9
internal register access 3-6
memory map example 5-2
PCI Target 1-3, 1-5, 3-1, 4-1–4-7, 10-35
PCISR 10-5
pin information 11-1
PMCSR 10-13
power management 7-1
prefetch 4-3
programmable 1-3
Read Ahead mode, PCI Target 4-3
READY# Timeout 10-34
serial EEPROM 3-1
signaling 1-4, 1-5
soft reset 7-2
VPD 9-1
width 1-1, 4-7
13-6
base address registers 10-8–10-9
Local Bus region descriptor registers 2-4, 4-5,
local chip selects
lock 4-1
LOCK# 10-35, 11-7, 13-3, 13-6
LPMESET 11-2, 11-11, 13-3, 13-6
LPMINT# 6-2, 11-11, 13-3, 13-6
LREQ 2-5, 11-2, 11-11, 13-3, 13-6
LRESETo# 3-1, 11-11, 13-3, 13-6
LW/R# 2-4, 11-14, 11-16, 13-3, 13-6
M
map
mapping
Master Abort, not supported 10-5
maximum ratings 12-1
memory
address mapping 10-3
See chip select
atomic operations 11-9
CNTRL 10-35
cycles 1-5
LLOCKo# 2-4, 11-3, 11-9, 13-3, 13-6
LOCK# 10-35, 11-7, 13-3, 13-6
PCI Target enable 10-35
memory 5-2
PCI software 4-5
PCI Target 1-3
read accesses 4-4
registers 3-7
serial EEPROM memory 3-2
See Also mapping and remap
address 4-3
expansion ROM local base address register 10-20
local address space local base address registers 10-19–
local registers 4-1
memory, prefetchable 2-1–2-2
register address 10-2–10-3
accesses 2-9, 3-6, 3-7, 10-2, 10-7, 10-8, 10-9
address spaces 10-16, 10-17, 10-19, 10-20
BTERM# 2-9
burst memory-mapped 1-3
commands aliased to basic 2-1
cycle 3-7
disabled 7-1
local controller 2-8
local spaces 1-3
map example 5-2
mapping, prefetchable 2-1–2-2
PCI 4-4, 7-2, 10-13
posted writes (PMW) 1-3
read 2-1, 4-4
10-21–10-29, 11-14, 11-17
10-20
to memory
LD[31:0]
Index-5