PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 52

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

Section 4
PCI Target (Direct Slave) Operation
during PCI Target Write transactions, the PCI 9030
empties the Write FIFO by dumping the data into the
Local Bus and does not pass an error condition to the
PCI
transactions, the PCI 9030 issues a PCI Target Abort
to the PCI Bus Initiator every time the PCI Target
Local Bus READY# Timeout is detected.
4.2.1.7
A PCI Bus Master addressing the Memory space
decoded for the Local Bus initiates transactions. Upon
a PCI Read/Write, the PCI 9030 being a Local Bus
Master executes a transfer, at which time it reads data
into the PCI Target Read FIFO or writes data to the
Local Bus.
For a PCI Direct access to the Local Bus, the
PCI 9030 has a 32-Lword (128-byte) Write FIFO
and an 16-Lword (64-byte) Read FIFO. The FIFOs
enable the Local Bus to operate independently of the
PCI Bus.
For Write transfers, if the Write FIFO becomes full, the
PCI 9030 is programmable to disconnect, or retain the
PCI Bus while generating wait states (TRDY#
de-asserted) (CNTRL[18]).
For PCI Read transactions from the Local Bus, the
PCI 9030 holds off TRDY# while gathering data from
the Local Bus. For Read accesses mapped to PCI
Memory space, the PCI 9030 prefetches up to
16 Lwords (in Continuous Prefetch mode) from the
Local Bus. Unused Read data is flushed from the
FIFO. For Read accesses mapped to PCI I/O space,
the PCI 9030 does not prefetch Read data. Rather, it
breaks each read of a Burst cycle into a single
Address/Data cycle on the Local Bus.
The
(CNTRL[22:19]) can be used to program the period of
time in which the PCI 9030 holds off TRDY#. The
PCI 9030 issues a Retry to the PCI Bus Transaction
Master when the programmed time period expires.
This occurs when the PCI 9030 cannot gain Local Bus
control and return TRDY# within the programmed time
period or the Local Bus is slowly emptying the Write
FIFO, and filling the Read FIFO.
4-4
Bus
PCI
PCI Target Transfer
Initiator.
Target
Retry
During
Delay
PCI
Target
Clocks
Read
bits
The PCI 9030 supports on-the-fly Endian conversion
for Spaces 0, 1, 2, and 3, and Expansion ROM. The
Local Bus can be Big/Little Endian by using the
programmable internal register configuration.
Note:
Figure 4-3. PCI Target Write
Figure 4-4. PCI Target Read
Note:
4.2.1.8
Five Local Address spaces—Spaces 0, 1, 2, and 3,
and Expansion ROM—are accessible from the PCI
Bus. Each is defined by a set of three registers:
• Local Address Range (LASxRR and/or EROMRR,
• Local Base Address (LASxBA and/or EROMBA)
• PCI Base Address (PCIBAR2, PCIBAR3,
where x is the Local Address Space number)
PCIBAR4, PCIBAR5, and/or PCIERBAR)
Master
Master
The PCI Bus is always Little Endian.
The figures represent a sequence of Bus cycles.
IRDY#, AD (data)
DEVSEL#, TRDY#
FRAME#, C/BE#,
FRAME#, C/BE#,
TRDY#, AD (data)
© 2002 PLX Technology, Inc. All rights reserved.
DEVSEL#
AD (addr)
AD (addr)
IRDY#
PCI Target PCI-to-Local
Address Mapping
Slave
Slave
9030
9030
PCI
PCI
PCI 9030 Data Book Version 1.4
Direct Data Transfer Mode
Master
Master
LA, ADS#, LW/R#,
LA, ADS#, LW/R#
LAD, BLAST#
LRDYi#, LAD
BLAST#
LRDYi#
Slave
Slave