PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 187

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

Index
A
Abort, Master, not supported 10-5
Abort, Target 2-1, 10-5
absolute maximum ratings 12-1
AC electrical characteristics 12-3, 12-4
accelerator, I/O 1-1
accesses 1-4, 2-1, 2-10, 3-1, 4-4, 4-5, 10-4, 10-10,
AD[31:0] 11-7, 13-3, 13-6
adapter card
address
PCI 9030 Data Book Version 1.4
© 2002 PLX Technology, Inc. All rights reserved.
disabled 7-2, 7-3
Hot Swap 8-1, 8-2, 8-3
I/O 3-7, 10-13
internal register 3-6–3-7
Local Bus 2-6, 2-8, 2-10
memory 2-9, 3-6
PCI 2-1, 2-2, 4-1, 4-6, 4-7, 10-3, 10-19, 10-20, 10-35
Slave 1-3
TAP 11-18
VPD 9-1, 10-15, 10-33
CompactPCI 1-2
PMC 1-3
address-to-data 2-8
boundary 2-9
burst start 2-10
bus state 2-3
chip select base registers 10-31, 10-32
cycle 2-9, 2-10
decode 10-10, 10-18
EROMBA 10-20
invariance 2-1, 2-11
local address space bus region descriptor
local address space local base address registers 10-19–
local address space range registers 10-16–10-17
local bits 2-2
mapping 4-3, 4-4
Multiplexed and Non-Multiplexed Bus modes 11-1
Multiplexed Bus mode 11-12
Non-Multiplexed Bus mode 11-15
PCI 3-7, 4-3–4-7, 10-15
pointer 10-1
PROT_AREA 10-33
Read Ahead mode, PCI Target 4-3
10-11
base address registers 10-7–10-9
base address registers 10-7–10-9
system bus interface pins 11-7
registers 10-21–10-27
10-20
Address/Data 1-3, 2-3, 2-4, 2-6, 2-9, 4-4, 10-4, 11-13
ADS# 11-12, 11-15, 13-3, 13-6
ALE 2-4, 11-12, 11-15, 13-3, 13-6
arbitration, Local Bus 2-3, 2-5
architecture
asynchronous
atomic operations
B
B
back-to-back
BCLKo 11-9, 13-3, 13-6
BD_SEL# 8-1, 11-1, 11-6, 13-3, 13-6
Big Endian
BIOS 2-1, 3-6, 6-1, 7-1, 10-18
BLAST# 11-12, 11-15, 13-3, 13-6
board routing, µBGA 13-7–13-8
bridge architecture 2-2
BTERM# 2-8, 2-9, 11-1, 11-12, 11-15, 13-3, 13-6
buffers
bursts
0
register mapping 10-2–10-3
registers 1-5, 3-3, 4-1
spaces 1-1, 1-3, 1-5, 2-10, 5-1–5-2
stepping 10-4
VPD 9-1
timing diagram 2-6, 4-9
boundary scan 11-18
RISC and bridge 2-2
resets 1-2, 8-1
LLOCKo# 2-4, 11-3, 11-9, 13-3, 13-6
LOCK# 11-7, 13-3, 13-6
locked 4-1
-B
fast 10-4, 10-5
timing diagrams 4-23–4-26
See Endian, Big/Little
ENUM# three-state 11-2
I/O 1-2, 8-1, 8-2, 11-4
output 8-1, 11-5
Posted Memory Write (PMW), bridge 2-2
continuous mode 2-9–2-10
expansion ROM enable 10-29
last and terminate 11-12, 11-15
memory space enable 10-21–10-27
PCI 4-1, 4-3, 4-4
period device 10-11
read and write 11-7
timing diagrams 4-16–4-20, 4-29–4-31, 4-36–4-41
transfers 1-1, 1-3
3
power management states 7-1
Index-1