PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 131

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

Local Configuration Registers
Register 10-40. (LAS2RR; 08h) Local Address Space 2 Range
Register 10-41. (LAS3RR; 0Ch) Local Address Space 3 Range
PCI 9030 Data Book Version 1.4
© 2002 PLX Technology, Inc. All rights reserved.
31:28
31:28
27:4
27:4
Bit
Bit
2:1
2:1
0
3
0
3
Memory Space Indicator. Writing 0 indicates Local Address Space 2 maps
into PCI Memory space. Writing 1 indicates Local Address Space 2 maps into
PCI I/O space.
When mapped into Memory space, encoding is as follows:
00 = Locate anywhere in 32-bit PCI Address space
01 = PCI r2.1, Locate below 1-MB Memory Address space
10 = Locate anywhere in 64-bit PCI Address space
11 = Reserved
When mapped into I/O space, bit 1 must be set to 0.
Bit 2 is included with bits [27:3] to indicate the decoding range.
When mapped into Memory space, writing 1 indicates reads are prefetchable
(does not affect PCI 9030 operation, but is used for system status).
When mapped into I/O space, it is included with bits [27:2] to indicate the
decoding range.
Specifies which PCI Address bits to use for decoding a PCI access to Local
Address Space 2. Each bit corresponds to a PCI Address bit. Bit 27
corresponds to address bit 27. Write 1 to all bits that are to be included in
decode and 0 to all others (used in conjunction with PCIBAR4).
Notes: Range (not Range register) must be power of 2. “Range register
value” is two’s complement of range.
User should limit each I/O-mapped space to 256 bytes per PCI r2.2.
Reserved. (PCI Address bits [31:28] are always included in decoding.)
Memory Space Indicator. Writing 0 indicates Local Address Space 3 maps
into PCI Memory space. Writing 1 indicates Local Address Space 3 maps into
PCI I/O space.
When mapped into Memory space, encoding is as follows:
00 = Locate anywhere in 32-bit PCI Address space
01 = PCI r2.1, Locate below 1-MB Memory Address space
10 = Locate anywhere in 64-bit PCI Address space
11 = Reserved
When mapped into I/O space, bit 1 must be set to 0.
Bit 2 is included with bits [27:3] to indicate the decoding range.
When mapped into Memory space, writing 1 indicates reads are prefetchable
(does not affect PCI 9030 operation, but is used for system status).
When mapped into I/O space, it is included with bits [27:2] to indicate the
decoding range.
Specifies which PCI Address bits to use for decoding a PCI access to Local
Address Space 3. Each bit corresponds to a PCI Address bit. Bit 27
corresponds to address bit 27. Write 1 to all bits that are to be included in
decode and 0 to all others (used in conjunction with PCIBAR5).
Notes: Range (not Range register) must be power of 2. “Range register
value” is two’s complement of range.
User should limit each I/O-mapped space to 256 bytes per PCI r2.2.
Reserved. (PCI Address bits [31:28] are always included in decoding.)
PCI r2.2, Reserved
PCI r2.2, Reserved
Description
Description
Read
Read
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Write
Write
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Value after
Value after
Section 10
Reset
Reset
Registers
00
0h
0h
00
0h
0h
0
0
0
0
10-17