PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 50

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

Section 4
PCI Target (Direct Slave) Operation
4.2.1.2
The PCI 9030 can be programmed through the PCI
r2.2 Features Enable bit (CNTRL[14]) to perform all
PCI Read/Write transactions in compliance with PCI
r2.2. The following PCI 9030 behavior occurs when
CNTRL[14]=1.
4.2.1.2.1
PCI Bus single cycle aligned or unaligned PCI Target
Read transactions always result in a one-Lword single
cycle transfer on the Local Bus, with corresponding
Local Byte Enables (LBE[3:0]#), asserted to reflect
PCI Byte Enables (C/BE[3:0]#), unless the PCI Read
No Flush Mode bit is enabled (CNTRL[16]=1). (Refer
to Section 4.2.1.4.) This causes the PCI 9030 to Retry
all PCI Bus Read requests that follow, until the original
PCI Address and PCI Byte Enables (C/BE[3:0]#) are
matched. (Refer to Figure 4-1.)
Figure 4-1. PCI Target Delayed Read Mode
Note:
4-2
fetch Read data again
PCI Host returns to
PCI Host to “Retry”
PCI 9030 instructs
PCI Read request
PCI Bus is free to
Read data is now
Read cycle later
ready for Host
perform other
cycles during
PCI Bus
The figure represents a sequence of Bus cycles.
this time
PCI r2.2 Features Enable
PCI Target Delayed Read Mode
Features Enable
Internal registers
PCI 9030 returns
prefetched data
PCI 9030
Data is stored
Internal FIFO
in 16-Lword
immediately
bit set in
PCI r2.2
PCI 9030 requests
Read data from
Local Bus
Local memory
returns requested
data to PCI 9030
Local Bus
4.2.1.2.2
If the PCI Master does not complete the originally
requested PCI Target Delayed Read transfer, the
PCI 9030 flushes the PCI Target Read FIFO after
2
Target Read access. The PCI 9030 Retries all other
PCI Target Read accesses that occur before the
2
Flush Read FIFO bit is disabled (CNTRL[31]=0,
default). If enabled (CNTRL[31]=1), a new PCI Target
Read access flushes any pending delayed reads from
the Read FIFO and the new Read request is granted.
4.2.1.2.3
The PCI 9030 guarantees that if the first PCI Target
Write data cannot be accepted by the PCI 9030 and/or
the first PCI Target Read data cannot be returned by
the PCI 9030 within 16 PCI clocks from the beginning
of the PCI Target cycle (FRAME# asserted), the
PCI 9030 issues a Retry (STOP# asserted) to the
PCI Bus.
During successful PCI Target Read and/or Write
accesses, the subsequent data after the first access is
accepted for writes or returned for reads in eight PCI
clocks (TRDY# asserted). Otherwise, the PCI 9030
issues a PCI disconnect (STOP# asserted) to the
PCI Master.
In addition, setting the PCI r2.2 Features Enable bit
[CNTRL[14]=1) allows optional enabling of the
following PCI r2.2 functions:
• No write while a Delayed Read is pending
• Write and flush pending Delayed Read
15
15
(PCI Retries for writes) (CNTRL[17])
(CNTRL[15])
PCI clocks and grants an access to a new PCI
PCI Clock timeout, provided the Disconnect with
© 2002 PLX Technology, Inc. All rights reserved.
2
PCI r2.2 16- and 8-Clock Rule
15
PCI Clock Timeout
PCI 9030 Data Book Version 1.4
Direct Data Transfer Mode