PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 95

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

5
5.1
The PCI 9030 provides four chip select outputs to
selectively enable devices on its Local Bus. Each
active-low
independent of any local address space. Without this
feature, external address decoding logic is required to
implement chip selects.
5.2
There are four Chip Select Base Address registers.
These registers control the four chip select pins on
the PCI 9030. [For example, Chip Select 0 Base
Address register (CS0BASE) controls CS0#, Chip
Select 1 Base Address register (CS1BASE) controls
CS1#, and so forth.]
The Chip Select Base Address registers serve three
purposes:
The three rules used to program the Chip Select Base
Address registers are as follows:
PCI 9030 Data Book Version 1.4
© 2002 PLX Technology, Inc. All rights reserved.
1. To enable or disable chip select functions within
2. To set the range of the Local Bus Addresses
3. To set the Local Base Address, at which the
1. Range must be a power of 2 (only the most
2. Base address must be a multiple of the range
3. Address range must be encompassed by one
the PCI 9030. If enabled, the chip select signal
is active if the Local Bus Address falls within
the address specified by the range and base
address. If disabled, the chip select signal
is not active.
for which the chip select signal(s) is active.
range starts.
significant bit is 1).
or 0.
or more Local Address Spaces. Otherwise, the
chip select decoder does not see addresses
which have not been claimed by the PCI 9030
on behalf of a Local Address Space, and a chip
select is not asserted.
LOCAL CHIP SELECTS
OVERVIEW
CHIP SELECT BASE
ADDRESS REGISTERS
chip
select
is
programmable
and
Each 28-bit Chip Select Base Address register is
programmed, as listed in the following table.
Table 5-1. Chip Select Base Address Register
Signal Programming
The Y bit (bit 0) enables or disables the chip select
signal. X bits are used to determine the range and
base address of where the CS# pin is asserted.
To program the base and range, the X bits are set
as follows:
• Device length or range is specified by the first bit
• Base Address is determined by the bit(s) set above
Figure 5-1. Chip Select Base Address and Range
MSB=27
set above the Y bit. Determined by setting a bit
in the register, calculated by shifting the range
value (a power of 2) one bit to the right (range
divided by 2).
the Range bit. The address is not shifted from its
original value. The base address uses all bits in the
register above (to the left of) the range bit, and none
of the bits in the register at or below (to the right of)
the Range bit.
XXXX
Range—Address
(where x is the
at which CSx#
Chip selects are not bound to any particular
Local Address Space unless programmed
accordingly in the CSxBASE, LASxRR, and
LASxBA registers (where x is the Chip Select
number or Local Address Space number,
as appropriate).
Chip Select
is asserted
number)
XXXX
XXXX
{
XXXX
XXXX
0
FFFFFFFh
Base Address
XXXX
LSB=0
XXXY
5-1