PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 99

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

6
6.1
The PCI 9030 provides two Local interrupt input
pins (LINTi[2:1]) and a register bit in the Interrupt
Control/Status register (INTCSR[7]) that can optionally
trigger PCI interrupt INTA# output. The interrupt input
pins have an associated register bit to enable or
disable the pin (INTCSR[3, 0], respectively), and each
has a Status bit to indicate whether an interrupt source
is active (INTCSR[5, 2], respectively). The LINTi[2:1]
pins are programmable for active-low or active-high
polarity in the default Level-Sensitive mode. They can
be optionally configured as a rising edge-triggered
interrupt (such as, for ISA compatibility).
Level-sensitive interrupts are cleared when the
interrupt source is no longer active, or the interrupt
input
interrupts remain active until cleared by a software
write, which either asserts the associated Local Edge
Triggerable Interrupt Clear bit(s) (INTCSR[11:10],
respectively), or disables the interrupt input pin.
INTA# output can also be de-asserted by clearing the
PCI Interrupt Enable bit (INTCSR[6]=0).
6.2
Figure 6-1. Interrupt and Error Sources
6.2.1
A PCI 9030 PCI Interrupt (INTA#) can be asserted by
Local Interrupt Input 2 or 1 (LINTi[2:1]), which are
described in the next section. INTA# can also be
asserted by setting the Software Interrupt bit
(INTCSR[7]=1).
PCI 9030 Data Book Version 1.4
© 2002 PLX Technology, Inc. All rights reserved.
LINTi1
LINTi2
Software Interrupt
INTCSR[7]
pin
INTERRUPTS AND GENERAL PURPOSE I/O
OVERVIEW
INTERRUPTS
PCI Interrupts (INTA#)
is
disabled.
Edge-triggered
OR
(latched)
INTA#
INTA#
configuration) in the Interrupt Control/Status register
(INTCSR[6]). If a PCI interrupt is required, the PCI
Interrupt Pin register (PCIIPR) must be set to a value
of 1 at boot time by the serial EEPROM, or chip default
value 1 if a blank or no serial EEPROM is used, so that
BIOS can route INTA# to an interrupt controller
interrupt request (IRQ) input. BIOS writes the
assigned IRQ number to the PCI Interrupt Line register
(PCIILR). PCIILR register bit values are system-
architecture specific.
An INTA# assertion generated from either LINTi[2:1]
input, configured as level-sensitive interrupts, is
cleared when one of the following occurs:
• Interrupt source is no longer active
• Interrupt input pin is disabled
• PCI interrupts are disabled (INTCSR[6]=0)
Subsequent to disabling interrupts, if the Local
interrupt input remains asserted and interrupts are
re-enabled, another interrupt is generated.
An INTA# assertion generated from either LINTi[2:1]
input, configured as edge-triggered interrupts, remains
active regardless of the LINTi[2:1] input pin state, until
the interrupt is cleared with a software write that
performs one of the following:
• Asserts the associated Local Edge Triggerable
• Disables the interrupt input pin
• Disables PCI interrupts (INTCSR[6]=0)
Subsequent to disabling interrupts, if interrupts are
re-enabled,
(although the LINTi[2:1] input state remains high) until
the next low-to-high transition on the LINTi[2:1] input
pin occurs.
A software interrupt can be enabled by setting the
Software Interrupt bit (INTCSR[7]=1). INTA# is
asserted if the PCI Interrupt Enable bit is also set
(INTCSR[6]=1).
de-asserted when the Software Interrupt or PCI
Interrupt Enable bit is cleared (INTCSR[7 or 6]=0,
respectively).
Interrupt Clear bit(s) (INTCSR[11:10], respectively)
can
another
be
INTA#
enabled
interrupt
output
or
is
disabled
is
not
subsequently
generated
(default
6-1