PCI9030-AA60BI PLX Technology, PCI9030-AA60BI Datasheet - Page 36

• Manufacturer Part Number: PCI9030-AA60BI
• Description: Peripheral Drivers & Components (PCIs) 32-bit 33MHz PCI v.2.2-compliant
• Manufacturer: PLX Technology

Specifications of PCI9030-AA60BI

• Package / Case: FPBGA-180
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / Rohs Status: No RoHS Version Available

Section 2
PCI and Local Bus
the BTERM# input are enabled (LASxBRD[2]=1 and/
or EROMBRD[2]=1) and the BTERM# signal is
asserted, the PCI 9030 asserts BLAST# only if its
Read FIFO is full, its Write FIFO is empty, or a transfer
completes.
2.2.4.3.4
Partial Lword accesses are Lword accesses in which
not all byte enables are asserted.
PCI Target writes always pass the PCI Byte Enables
(C/BE[3:0]#) to the Local Byte Enables (LBE[3:0]#).
PCI Target Single reads always pass the Byte
Enables.
Enables and return all 32-bit data. (Refer to Table
2-8.)
Local Bus Burst Start addresses can be any Lword
boundary. If the Burst Start address in a PCI Target
transfer is not aligned to an Lword boundary, the
PCI 9030 first performs a single cycle. It then starts to
burst on the Lword boundary.
Table 2-8. PCI Target Single and Burst Reads
2.2.4.4
In Multiplexed mode, the PCI 9030 inserts a minimum
of one recovery state between the last Data transfer
and the next Address cycle. Add recovery states
by programming values greater than 1 into the
NXDA bits of the Bus Region Descriptor register(s)
(LASxBRD[14:13] and/or EROMBRD[14:13]).
In Non-Multiplexed mode, the PCI 9030 uses the
NXDA (data-to-address wait states) value in the Bus
Region Descriptor register(s) (LASxBRD[14:13] and/or
EROMBRD[14:13]) to determine the number of
recovery states to insert between the last Data transfer
and next Address cycle. This value can be
programmed between 0 and 3 clock cycles (default
value is 0).
Note:
uses the READY# input to add recovery states. No additional
recovery states are added if the READY# input remains asserted
during the last Data cycle.
2-10
32-, 16-, or 8-bit
Local Bus
Bus
The PCI 9030 does not support the i960J function that
PCI Target Burst reads ignore the Byte
Recovery States
Partial Lword Accesses
Passes the
byte enables
Single Reads
PCI Target
Ignores the byte
enables and all
32-bit data is passed
Burst Reads
PCI Target
2.2.4.5
For all single cycle Local Bus Read accesses, the
PCI 9030 reads only bytes corresponding to byte
enables requested by a PCI Initiator. For all Burst
Read cycles, the PCI 9030 can be programmed to:
• Perform PCI Target Delayed Reads
• Perform PCI Target Read Ahead
• Generate internal wait states
• Enable external wait control (READY# input)
• Enable type of Burst mode to perform
2.2.4.6
For Local Bus writes, only bytes specified by a
PCI Bus Master are written.
For all Burst Write cycles, the PCI 9030 can be
programmed to:
• Perform PCI Target delayed writes
• Generate internal wait states
• Enable external wait control (READY# input)
2.2.5
For each of the following transfer types, the PCI 9030
Local Bus can be independently programmed to
operate in Little Endian or Big Endian mode for PCI
Target accesses to Local Address Spaces 0, 1, 2, and
3, and Expansion ROM.
Notes:
Only byte lanes are swapped, not individual bits.
The PCI 9030 Local Bus can be programmed
to operate in Big or Little Endian mode, as listed in
Table 2-9.
Big/Little Endian Control bits are as follows:
• LAS0BRD[24]—Space 0
• LAS1BRD[24]—Space 1
• LAS2BRD[24]—Space 2
• LAS3BRD[24]—Space 3
• EROMBRD[24]—Expansion ROM
In Big Endian mode, the PCI 9030 transposes data
byte lanes. Data is transferred as listed in Table 2-10
through Table 2-14.
The PCI Bus is always Little Endian.
Local Bus Big/Little Endian Mode
© 2002 PLX Technology, Inc. All rights reserved.
Local Bus Read Accesses
Local Bus Write Accesses
PCI 9030 Data Book Version 1.4
Local Bus