TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 117

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

TA0REG (Value of compare)
TA0REG-WR
Match with TA0REG
Match withTA1REG
TA01RUN<TA0RDE>
Register buffer
each time the 8-bit up counter (UC0) matches the value in one of the timer registers
TA0REG or TA1REG.
Although the up counter for TMRA1 (UC1) is not used in this mode, TA01RUN<TA1RUN>
should be set to “1”, so that UC1 is set for counting.
be shifted into TA0REG each time TA1REG matches UC0.
TA0IN
TA01MOD<TA0CLK1:0>
In this mode, a programmable square wave is generated by inverting the timer output
The value set in TA0REG must be smaller than the value set in TA1REG.
Figure 3.7.14 shows a block diagram representing this mode.
φT16
If the TA0REG double buffer is enabled in this mode, the value of the register buffer will
Use of the double buffer facilitates the handling of low-duty waves (when duty is varied).
and UC0
Selector
φT1
φT4
Figure 3.7.14 Block Diagram of 8-Bit PPG Output Mode
Selector
Shift trigger
Figure 3.7.15 Operation of Register Buffer
Register buffer
Comparator
TA0REG
(Up counter = Q
Internal data bus
Q
up counter
1
(UC0)
92CM22-115
8-bit
2
)
Q
2
Comparator
TA1REG
TA01RUN<TA0RUN>
(Up counter = Q
Shift into register buffer
2
)
Q
2
Write TA0REG (Register buffer)
TA1OUT
TA1FF
Q
3
Inversion
INTTA0
INTTA1
TA1FFCR<TA1FFIE>
TMP92CM22
2007-02-16