TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 188

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

SCL line
SDA line
SCL
SDA
<PIN>
INTSBE0
interrupt
request
<PIN>
INTSBE0
interrupt
request
Figure 3.10.15 Example of when <BC2:0> = “000”, <ACK> = “1” (Receiver mode)
9
Figure 3.10.16 Termination of Data Transfer (Master receiver mode)
read the received data from SBI0DBR to release the SCL line (Data which is read
immediately after a slave address is sent is undefined). After the data is read,
<PIN> becomes “1”. Serial clock pulse for transferring new 1 word of data is
defined SCL and outputs “L” level from SDA pin with acknowledge timing.
Read receiving data
the TMP92CM22 pulls down the SCL pin to the low level. The TMP92CM22
outputs a clock pulse for 1 word of data transfer and the acknowledge signal each
time that received data is read from the SBI0DBR.
“0” before reading data which is 1 word before the last data to be received. The last
data word does not generate a clock pulse as the acknowledge signal. After the
data has been transmitted and an interrupt request has been generated, set
<BC2:0> to “001” and read the data. The TMP92CM22 generates a clock pulse for
a 1-bit data transfer. Since the master device is a receiver, the SDA line on the bus
remains high. The transmitter receives the high signal as an ACK signal. The
receiver indicates to the transmitter that the data transfer is completed.
generated, the TMP92CM22 generates a stop condition (See section 3.10.6 (4)) and
terminates data transfer.
When the <TRX> is “0” (Receiver mode)
D7
D7
When the next transmitted data is other than 8 bits, set <BC2:0> <ACK> and
1
1
An INTSBE interrupt request then generates and the <PIN> becomes “0”, Then
In order to terminate the transmission of data to a transmitter, clear <ACK> to
After the one data bit has been received and an interrupt request has been
After clear <ACK> to “0”, reading receiving data.
D6
D6
2
2
D5
D5
3
3
92CM22-186
D4
D4
4
4
D3
D3
5
5
D2
D2
6
6
D1
D1
7
7
D0
D0
8
8
ACK
Output of master
Output of slave
9
1
Acknowledge signal
“H” to transmitter
After set “001” to
<BC2:0>, reading
receiving data.
Acknowledge signal to
a transmitter
Output of master
Output of slave
TMP92CM22
New D7
2007-02-16