TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 187

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

SCL line
SDA line
<PIN>
INTSBE0
interrupt
request
SCL Pin
SDA Pin
<PIN>
INTSBE0
interrupt
request
Figure 3.10.14 Example in which <BC2:0> = “000” and <ACK> = “1” (Transmitter mode)
(3) 1-word data transfer
is completed, and determine whether the mode is a master or slave.
When the <TRX> = “1” (Transmitter mode)
1.
Check the <MST> by the INTSBE0 interrupt process after the 1-word data transfer
Check the <TRX> and determine whether the mode is a transmitter or receiver.
Start condition
Figure 3.10.13 Start Condition and Slave Address Generation
If <MST> = “1” (Master mode)
Implement the process to generate a stop condition (Refer to 3.10.6 (4)) and
terminate data transfer.
transmitted data is 8 bits, write the transmitted data to SBI0DBR. When the next
transmitted data is other than 8 bits, set the <BC2:0> <ACK> and write the
transmitted data to SBI0DBR. After written the data, <PIN> becomes “1”, a serial
clock pulse is generated for transferring a new 1-word of data from the SCL pin,
and then the 1-word data is transmitted. After the data is transmitted, an
INTSBE interrupt request generates. The <PIN> becomes “0” and the SCL line is
pulled down to the low level. If the data to be transferred is more than one word in
length, repeat the procedure from the <LRB> checking above.
Write to SBI0DBR
D7
Check the <LRB>. When <LRB> is “1”, a receiver does not request data.
When the <LRB> is “0”, the receiver is requests new data. When the next
1
A6
1
D6
2
A5
2
D5
3
A4
3
Slave address + Direction bit
92CM22-185
D4
4
A3
4
D3
5
A2
5
D2
6
A1
6
D1
7
A0
7
D0
8
R/
8
W
ACK
9
Output of master
Output of slave
ACK
Acknowledge signal
from a receive
Output of master
Output of slave
9
TMP92CM22
Acknowledge
signal from a
slave device
2007-02-16