TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 246

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

SC0MOD0
SC0MOD1
Symbol
BR0ADD
SC0BUF
SC0CR
BR0CR
SIRCR
(8) UART/Serial channel (1/2)
channel 0
channel 0
channel 0
channel 0
channel 0
channel 0
baud rate
K setting
Name Address
register
register
mode 0
register
register
register
mode 1
register
register
control
control
control
Serial
buffer
Serial
Serial
Serial
Serial
Serial
IrDA
(Prohibit
1200H
1201H
1202H
1203H
1204H
1205H
1207H
RMW)
Receive
data
bit8
Transmis-
sion data
bit8
Always
write “0”.
IDLE2
Select
transmit
pulse
width
Undefined
0: Stop
1: Operate
0: 3/16
1: 1/16
PLSEL
I2S0
RB7
RB8
TB7
TB8
7
R
0
−
0
0
0
R/W
0: “H” pulse
1: “L” pulse
BR0ADDE BR0CK1
1: Full duplex
Parity
0: CTS
1: CTS
(16 − K)/
16 divided
I/O interface
mode
0: Half duplex
Receive
data
0: Odd
1: Even
0: Disable
1: Enable
RXSEL
FDPX0
enable
EVEN
disable
CTSE
RB6
TB6
6
0
0
0
0
0
92CM22-244
R/W
00: φT0
01: φT2
10: φT8
11: φT32
0: Disable
1: Enable
Parity
0: Receive
1: Receive
Transmit
0: Disable
1: Enable
enable
disable
TXEN
RB5
RXE
TB5
PE
5
0
0
0
0
R(Receiving) / W(Transmission)
1: Enable
0: Disable
Wake up
Receive
0: Disable
1: Enable
BR0CK0
Overrun
OERR
RXEN
RB4
TB4
WU
4
0
0
0
0
R (Clear o after reading)
Undefined
R/W
R/W
R/W
Select receive pulse width
Set effective pulse width for equal or more
than 2x × (Value + 1) + 100 ns
Can be set: 1 to 14
Can not be set: 0, 15
00: I /O interface mode
01: 7-bit UART mode
10: 8-bit UART mode
11: 9-bit UART mode
SIRWD3
1: Error
BR0S3
BR0K3
PERR
Parity
SM1
RB3
TB3
3
0
0
0
0
0
(divided by N + (16 − K)/16).
Sets frequency divisor “K”
Divided frequency setting
SIRWD2
Framing
BR0S2
BR0K2
FERR
SM0
RB2
TB2
2
0
0
0
0
0
R/W
0: SCLK0↑
1: SCLK0↓
00: Timer TA0REG
01: Baud rate
10: Internal clock fio
11: External clock
SIRWD1
SCLKS
BR0S1
BR0K1
RB1
TB1
SC1
generator
(SCLK0 input)
1
0
0
0
0
0
TMP92CM22
R/W
2007-02-16
1: SCLK0 pin
0: Baud
SIRWD0
BR0S0
BR0K0
rate
generator
input
RB0
SC0
TB0
IOC
0
0
0
0
0
0