TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 169

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

Protocol
1.
2.
3.
4.
5.
6.
Select 9-bit UART mode on the master and slave controllers.
Set the SC0MOD0<WU> bit on each slave controller to 1 to enable data receiving.
The master controller transmits one-frame data including the 8-bit select code for
the slave controllers. The MSB (Bit8) <TB8> is set to “1”.
Each slave controller receives the above frame. If it matches with own select code,
clears <WU> bit to “0”.
The master controller transmits data to the specified slave controller whose
SC0MOD0<WU> bit is cleared to “0”. The MSB (Bit8) <TB8> is cleared to “0”.
The other slave controllers (whose <WU> bits remain at 1) ignore the received
data because their MSB (Bit8 or <RB8>) are set to “0”, disabling INTRX0
interrupts. The slave controller (<WU> bit = “0”) can transmit data to the master
controller, and it is possible to indicate the end of data receiving to the master
controller by this transmission.
Start
Start
Bit0
Bit0
1
1
Select code of slave controller
92CM22-167
2
2
3
3
Data
4
4
5
5
6
6
7
7
Bit8
“0”
“1”
8
Stop
Stop
TMP92CM22
2007-02-16