TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 27

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

releasing halt
releasing halt
Interrupt of
D0 to D15
A0 to A23
Interrupt of
D0 to D15
A0 to A23
(3) Operation
Figure 3.3.6 Timing Chart for IDLE2 Mode Halt State Released by Interrupt
Figure 3.3.7 Timing Chart for IDLE1 Mode Halt State Released by Interrupt
WR
RD
X1
WR
RD
X1
IDLE2 setting register, can take place. Instruction execution by the CPU stops.
mode halt state by an interrupt.
register. Table 3.3.5, Table 3.3.6 shows pin state in IDLE1 mode.
system clock; however, clearance of the halt state (e.g., restart of operation) is
synchronous with it.
interrupt.
a. IDLE2 mode
b. IDLE1 mode
In IDLE2 mode only specific internal I/O operations, as designated by the
Figure 3.3.6 illustrates an example of the timing for clearance of the IDLE2
In IDLE1 mode, only the internal oscillator operates. The system clock stops.
And, pin state in IDLE1 mode depend on setting SYSCR2<SELDRV, DRVE>
In the halt state, the interrupt request is sampled asynchronously with the
Figure 3.3.7 shows the timing for release of the IDLE1 mode halt state by an
Data
Data
92CM22-25
IDLE2
mode
IDLE1
mode
TMP92CM22
2007-02-16
Data
Data