TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 78

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

(003CH)
(003EH)
(003EH)
(003FH)
(003FH)
PFCR
PFCR
PFFC
PFFC
PF
<PF3F>
<PF0F>
Port function setting
Bit symbol
Read/Write
After reset
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
<PF3C>
<PF0C>
0
1
0
1
Note 1: Read-modify-write instruction is prohibited for the registers PFCR and PFFC.
Note 2: PF1/RXD0 and PF4/RXD1 pins do not have a register changing PORT/FUNCTION. For example, when it is
Note 3: PF0 and PF3 pins do not have a register (PFODE) for open-drain setting. Please conduct the open-drain
used as an input port, the input signal is inputted to SIO as the serial receive data.
setting according to above setting.
(Open drain)
(Open drain)
Input port
Input port
Always
write “0”.
TXD1
TXD0
PF7C
0
0
PF7
7
7
7
0
−
0
Always
write “0”.
Output port
Output port
PF6C
PF6
TXD1
TXD0
W
6
6
6
0
0
−
1
1
Figure 3.5.29 Register for Port F
Data from external port (Output latch register is set to 1)
0: Port
1: SCLK1
Port F Function Register
Port F Control Register
PF5C
PF5F
output
PF5
5
5
5
0
0
Port F Register
92CM22-76
0: Input
PF4C
PF4
4
4
4
0
R/W
W
0: Port
1: TXD1
1: Output
PF3C
PF3F
PF
3
3
3
0
0
W
0: Port
1: SCLK0
PF2C
PF2F
output
PF2
2
2
2
0
0
PF1C
PF1
1
1
1
0
0: Port
1: TXD0
PF0C
PF0F
TMP92CM22
PF0
W
0
0
0
0
0
2007-02-16