TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 179

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

Read-
modify-write
instruction is
prohibited.
Read-
modify-write
instruction is
prohibited.
Read-
modify-write
instruction is
prohibited.
Read-
modify-write
instruction is
prohibited.
SBI0BR0
(1244H)
SBI0BR1
(1245H)
I2C0AR
(1242H)
SBI0DBR
(1241H)
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Note 1: When writing transmission data, start from the MSB (Bit7). Receiving data is placed from LSB (Bit0).
Note 2: SBI0DBR can’t be read the written data. Therefore read-modify-write instruction (e.g., “BIT” instruction) is
prohibited.
Always
write “0”.
Internal
clock
0: Stop
1: Run
P4EN
SA6
DB7
W
7
7
7
−
0
0
0
7
W
Slave address selection for when device is operating as slave device
Serial Bus Interface Baud Rate Register 0
IDLE2
0: Stop
1: Run
Serial Bus Interface Baud Rate Register 1
Always
write “0”.
Figure 3.10.6 Register for I
Sirial Bus Interface Data Buffer Register
I2SBI0
R/W
SA5
DB6
6
6
6
0
−
0
0
6
I
2
C Bus Address Register
92CM22-177
SA4
DB5
5
5
5
0
5
R (Receiving)/W (Transmission)
SA3
DB4
4
4
4
0
4
2
Undefined
C Bus Mode
W
SA2
DB3
3
3
3
0
3
Address recognition mode specification
Operation during IDLE 2 mode
Operation during IDLE 2 mode
0
1
0
1
0
1
SA1
DB2
2
2
2
0
2
Stop
Run
Stop
Run
Slave address recognition
Non slave address recognition
SA0
DB1
1
1
1
0
1
TMP92CM22
2007-02-16
Address
recognition
mode
specification
ALS
DB0
0
0
0
0
0