TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 167

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

(2) Mode 1 (7-bit UART mode)
(3) Mode 2 (8-bit UART mode)
SC0MOD
SC0CR
BR0CR
INTES0
SC0BUF
X : Don’t care, − : No change
Main routine
PFCR
SC0MOD
SC0CR
BR0CR
INTES0
Interrupt routine processing
Acc
X : Don’t care, − : No change
PFCR
PFFC
Acc
if Acc
SC0MOD0<SM1:0> to 01.
the setting of the serial channel control register SC0CR<PE> bit; whether even parity
or odd parity will be used is determined by the SC0CR<EVEN> setting when
SC0CR<PE> is set to 1 (Enabled).
parity bit can be added (Use of a parity bit is enabled or disabled by the setting of
SC0CR<PE>); whether even parity or odd parity will be used is determined by the
SC0CR<EVEN> setting when SC0CR<PE> is set to 1 (Enabled).
Example: When transmitting data of the following format, the control registers should be
Example: When receiving data of the following format, the control registers should be set
7-bit UART mode is selected by setting serial channel mode register
In this mode, a parity bit can be added. Use of a parity bit is enabled or disabled by
8-bit UART mode is selected by setting SC0MOD0<SM1:0> to 10. In this mode, a
Start
← − − − − − − − 1
← − − − − − − − 1
← X 0 − X 0 1 0 1
← X 1 1 X X X 0 0
← 0 0 1 0 1 0 0 0
← 1 1 0 0 − − − −
← ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗
← − − − − − − 0 −
← − 0 1 X 1 0 0 1
← X 0 1 X X X 0 0
← 0 0 0 1 1 0 0 0
← − − − − 1 1 0 0
← SC0CR AND 00011100
← SC0BUF
≠
Start
set as described below. This explanation applies to channel 0.
as described below.
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
0 then ERROR
Bit0
Bit0
Transfer direction (Transfer speed 9600 bps at f
1
Transfer direction (Transfer speed 2400 bps at f
1
2
92CM22-165
2
* Clock state:
* Clock state:
3
3
4
4
Set PF0 to as TXD0 pin.
Set to 7-bit UART mode.
Add even parity.
Set to 2400 bps.
Set INTTX0 interrupt to enable, set to level 4.
Set transmission data.
Set PF1 (RXD0) to input pin.
Set to 8-bit UART mode, set receives to enable.
Add odd parity.
Set to 9600 bps.
Set INTTX0 interrupt to enable, set to level 4.
Check for error.
Read receiving data.
Clock gear 1/1(fc)
Clock gear 1/1(fc)
5
5
6
6
7
C
parity
Even
= 39.3216 MHz)
C
parity
Odd
= 39.3216 MHz)
Stop
Stop
TMP92CM22
2007-02-16