TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 160

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

BR0CR
(1203H)
BR0ADD
(1204H)
Note1:Availability of +(16-K)/16 division function
Note2:Set BR0CR <BR0ADDE> to 1 after setting K (K = 1 to 15) to BR0ADD<BR0K3:0> when + (16-K)/16 division function
+ (16 − K)/16 divisions enable
Bit symbol
Read/Write
After reset
Function
Bit symbol
Read/Write
After reset
Function
BR0ADD
<BR0K3:0>
0
1
The baud rate generator can be set to “1” in UART mode only when the +(16-K)/16 division function is not used. Do not
1111 (K = 15)
is used. Writes to unused bits in the BR0ADD register do not affect operation, and undefined data is read from these
unused bits.
Figure 3.9.11 Baud Rate Generator Control (for SIO0, BR0CR, and BR0ADD)
0001 (K = 1)
use in I/O interface mode.
Disable
Enable
0000
BR0CR
<BR0S3:0>
Always
write “0”.
N
2 to 15
1 , 16
7
7
−
0
+ (16 − K)/16
division
0: Disable
1: Enable
BR0ADDE
0000 (N = 16)
Sets baud rate generator frequency divisor
0001 (N = 1)
UART mode
Disable
Disable
6
6
0
BR0CR<BR0ADDE> = 1
or
○
×
Setting the input clock of baud rate generator
00: φT0
01: φT2
10: φT8
11: φT32
00
01
10
11
BR0CK1
92CM22-158
5
5
0
Internal clock φT0
Internal clock φT2
Internal clock φT8
Internal clock φT32
N + (16-K) /16
1111 (N = 15)
0010 (N = 2)
I/O mode
Divided by
Disable
BR0CK0
×
×
4
4
0
R/W
BR0S3
BR0K3
3
3
0
0
BR0CR<BR0ADDE> = 0
0001 (N = 1) (UART only)
(Divided by N + (16 − K)/16).
Sets frequency divisor “K”
1111 (N = 15)
0000 (N = 16)
Divided frequency setting
Divided by N
BR0S2
BR0K2
2
2
0
0
R/W
BR0S1
BR0K1
1
1
0
0
TMP92CM22
BR0S0
BR0K0
2007-02-16
0
0
0
0