TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 136

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

Match with TB0RG0H/L
(INTTB00 interrupt )
Match with TB0RG1H/L
(INTTB01 interrupt)
Match with TB0RG1H/L
Match with TB0RG0H/L
(3) 16-bit programmable pulse generation (PPG) output mode
TB0OUT0 pin
TB0RG0H/L
(Compare value)
Register buffer 10
Figure 3.8.9 Programmable Pulse Generation (PPG) Output Waveforms
pulse may be either low active or high active.
enabled by the match of the up counter UC10 with timer register TB0RG0H/L or
TB0RG1H/L and to be output to TB0OUT0. In this mode, the following conditions must
be satisfied.
buffer 10 will be shifted into TB0RG0H/L at match with TB0RG1H/L. This feature
makes easy the handling of low-duty waves.
Square wave pulses can be generated at any frequency and duty ratio. The output
The PPG mode is obtained by inversion of the timer flip-flop TB0FF0 that is to be
(Set value of TB0RG0H/L) < (Set value of TB0RG1H/L)
When the TB0RG0H/L double buffer is enabled in this mode, the value of register
Figure 3.8.10 Operation of Register Buffer
Up counter = Q
Q
1
92CM22-134
1
Q
2
Shift in to TB0RG1H/L
Up counter = Q
Write TB0RG0H/L
Q
2
2
Q
3
TMP92CM22
2007-02-16