TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 185

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

(14) Software reset function
(15) Serial bus interface data buffer register (SBI0DBR)
(16) I
(17) Baud rate register (SBI0BR1)
(18) Setting register for IDLE2 mode operation (SBI0BR0)
by external noises, etc.
serial bus interface circuit, and circuit is initialized. All command registers except
SBI0CR2<SBIM1:0> and status flag except SBI0CR2<SBIM1:0> are initialized to
value of just after reset. SBI0CR1<SWRMON> is set to “1” automatically when
completed initialization of serial bus interface.
writing SBI0DBR.
register, the start condition is generated.
a slave device.
I2C0AR<ALS> to “0”. And, the data format becomes the addressing format. When set
<ALS> to “1”, the slave address is not recognized, the data format becomes the free
data format.
Therefore, setting <I2SBI0> is necessary before the HALT instruction is executed.
2
C bus address register (I2C0AR)
The software reset function is used to initialize the SBI circuit, when SBI is rocked
When write first “10” next “01” to SBI0CR2<SWRST1:0>, reset signal is inputted to
The received data can be read and transmission data can be written by reading or
In the master mode, after the slave address and the direction bit are set in this
I2C0AR<SA6:0> is used to set the slave address when the TMP92CM22 functions as
The slave address outputted from the master device is recognized by setting the
Write “1” to baud rate circuit control register SBI0BR1<P4EN> before using I
SBI0BR0<I2SBI0> is the register setting operation/stop during IDLE2 mode.
92CM22-183
TMP92CM22
2007-02-16
2
C bus.