TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 184

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

Master
Master
Accessed to
SBI0DBR or SBI0CR2
A
B
Figure 3.10.12 Example of when TMP92CM22 is a Master Device B (D7A = D7B, D6A = D6B)
Internal SCL
output
Internal SDA
output
Internal SCL
output
Internal SDA
output
<AL>
<MST>
<TRX>
(11) Slave address match detection monitor
(12) GENERAL CALL detection monitor
(13) Last received bit monitor
internal SDA output on the rising edge of the SCL line. If the levels do not match,
arbitration is lost and SBI0SR<AL> is set to “1”.
mode is switched to slave receiver mode. Thus, clock output is stopped in data transfer
after setting <AL> = “1”.
when data is written to SBI0CR2.
(e.g., when I2C0AR<ALS> = “0”), when received GENERAL CALL or same slave
address with value set to I2C0AR, SBI0SR<AAS> is set to “1”. When <ALS> = “1”,
SBI0SR<AAS> is set to “1” after the first word of data has been received.
SBI0SR<AAS> is cleared to “0” when data is written to SBI0DBR or read from
SBI0DBR.
CALL (all 8-bit data is “0”, after a start condition), SBI0SR<AD0> is set to “1”. And
SBI0SR<AD0> is cleared to “0” when a start condition or stop condition on the bus is
detected.
SBI0SR<LRB>. In the acknowledge mode, immediately after an INTSBE0 interrupt
request has been generated, an acknowledge signal is read by reading the contents of
the SBI0SR<LRB>.
The TMP92CM22 compares the levels on the bus’s SDA line with those of the
When SBI0SR<AL> is set to “1”, SBI0SR<MST, TRX> are cleared to “00” and the
SBI0SR <AL> is cleared to “0” when data is written to or read from SBI0DBR or
SBI0SR<AAS> operates following in during slave mode; In address recognition mode
SBI0SR<AD0> operates following in during slave mode; when received GENERAL
The value on the SDA line detected on the rising edge of the SCL line is stored in the
D7A
D7B
1
1
D6A
D6B
2
2
D5A
3
3
Keep internal SDA output to high level as losing arbitration
D4A
4
4
92CM22-182
D3A
Stop the clock pulse
5
D2A
6
D1A
7
D0A
8
9
D7A’
1
D6A’
2
TMP92CM22
2007-02-16
D5A’
3
D4A’
4