TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 26

• Manufacturer Part Number: TMP92xy22FG
• Manufacturer: Toshiba

Specifications of TMP92xy22FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 32
• Architecture: 32-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: -
• Adc 10-bit Channel: 8
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: -
• Number Of I/o Ports: 50
• Power Supply Voltage(v): 3.0 to 3.6

♦:
○
×:
−:
*1:
Note 1: When the HALT mode is released by INT0 to INT3 interrupts of the level mode in the interrupt
Note 2: When use external interrupt INT4 to INT5 are used during IDLE2 mode, set 16-bit timer RUN
Status of Received Interrupt
:
NMI
INTWDT
INT0 to 3 (Note1)
INT4 to 5
INTTA0 to 3,
INTTB00, 01, 10, 11, O0, O1
INTRX0 to 1, TX0 to 1
INTAD
INTSBE0
After release the HALT mode, CPU starts interrupt processing.
After release the HALT mode, CPU resumes executing starting from instruction following the HALT
instruction. (Interrupt don’t process.)
It can not be used to release the HALT mode.
The priority level (Interrupt request level) of non-maskable interrupts is fixed to 7, the highest priority
level. There is not this combination type.
Release the HALT mode is executed after passing the warm-up time.
enabled status, hold this level until starting interrupt processing. Changing level before holding level,
interrupt processing is correctly started.
register TB1RUN<I2TB1> to “1”.
HALT Mode
Reset
Table 3.3.3 Source of Halt State Release and Halt Release Operation
Address
8203H
8206H
8209H
820BH
820EH
INT0
820FH
(Example release HALT mode)
An INT0 interrupt release the halt state when the device is in IDLE1 mode.
LD
LD
EI
LD
HALT
LD
Programmable IDLE2
(IIMC), 00H
(INTE0AD), 06H
5
(SYSCR2), 28H
XX, XX
(Interrupt level) ≥ (Interrupt mask)
♦
♦
♦
♦
♦
♦
♦
♦
♦
Interrupt Enable
92CM22-24
;
;
;
;
;
IDLE1
♦
♦
×
×
×
×
×
×
×
Selects INT0 interrupt rising edge.
Sets INT0 interrupt level to 6.
Sets CPU interrupt level to 5.
Sets HALT mode to IDLE1 mode.
Halts CPU.
STOP
♦*1
♦
×
×
×
×
×
×
×
Initialize LSI
INT0 interrupt routine
Programmable IDLE2
(Interrupt level) < (Interrupt mask)
RETI
○
−
−
×
×
×
×
×
×
Interrupt Disable
IDLE1
TMP92CM22
○
−
−
×
×
×
×
×
×
2007-02-16
STOP
○
−
−
×
×
×
×
×
×
*1