TMP92xy22FG Toshiba, TMP92xy22FG Datasheet - Page 177

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TMP92xy22FG

Manufacturer Part Number
TMP92xy22FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP92xy22FG

Package
LQFP100
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
32
Architecture
32-bit CISC
Usb/spi Channels
-
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
-
Adc 10-bit Channel
8
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
2
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
-
Number Of I/o Ports
50
Power Supply Voltage(v)
3.0 to 3.6
Read-
modify-write
instruction is
prohibited.
SBI0CR2
(1243H)
Bit symbol
Read/Write
After reset
Function
Note 1: Reading this register function as SBI0SR register.
Note 2: Switch a mode to port mode after confirming that the bus is free.
Switch a mode between I
signals via port are high level.
Master/
slave
selection
MST
7
0
Figure 3.10.4 Register for I
Transmitter/
receiver
selection
Serial Bus Interface Control Register 2
TRX
6
0
2
C bus mode and clocked-synchronous 8-bit SIO mode after confirming that input
W
Start/stop
condition
generation
92CM22-175
BB
5
0
Release
INTSBE0
interrupt
request
Serial bus interface operating mode selection (Note 2)
INTSBE0 interrupt request
Start/stop condition generation
Transmitter/receiver selection
Master/slave selection
00
01
10
11
0
1
0
1
0
1
0
1
PIN
4
1
2
Port mode (Serial bus interface output disabled)
Clocked-synchronous 8-bit SIO mode
I
(Reserved)
Release interrupt request
Generates the stop condition
Generates the start condition
Receiver
Transmitter
Slave
Master
C Bus Mode
2
C bus mode
Serial bus interface
operation mode selection
(Note 2)
00: Port mode
01: SIO mode
10: I
11: (Reserved)
SBIM1
2
3
0
C bus mode
W (Note 1)
SBIM0
2
0
Software reset control
write “10” and “01” in
order, then an internal
software reset signal is
generated.
SWRST1
1
0
W (Note 1)
TMP92CM22
2007-02-16
SWRST0
0
0

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