CD2401 Intel, CD2401 Datasheet - Page 114

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

CD2401 — Multi-Protocol Communications Controller
8.3.1.2
114
Register Name: RCOR
Register Description: Receive Clock Option
Default Value: x’00
Access: Byte Read/Write
TLVal
Bit 7
Note: See the detailed description of the clock options in
Receive Clock Option Register (RCOR)
This register is used to select the DPLL mode and the desired clock source for the receive BRG.
Bit 7
Bit 6
Bit 5
Bits 4:3
Bits 2:0
Bit 6
0
Transmit Line Value
This reflects the logical value of the transmit data pin.
Reserved – must be ‘0’.
DPLL Enable
1 = DPLL is enabled
0 = DPLL is disabled
DPLL Mode select [1:0]
These bits select the type of data encoding used.
Clock Select [2:0]
These three bits select the clock source for the receive BRG or DPLL.
DpllEn
Bit 5
Dpllmd1
clkSel2
0
0
1
1
0
0
0
0
1
1
1
1
Dpllmd1
Bit 4
Dpllmd0
0
1
0
1
clkSel1
0
0
1
1
0
0
1
1
Dpllmd0
Bit 3
NRZ
NRZI
Manchester
Reserved
Section 5.5 on page
clkSel0
Encoding
0
1
0
1
0
1
0
1
ClkSel2
Bit 2
Clk 0
Clk 1
Clk 2
Clk 3
Clk 4
Reserved
External clock
Reserved
Clock Source
58.
Motorola Hex Address: x’C8
ClkSel1
Bit 1
Intel Hex Address: x’CA
Datasheet
ClkSel0
Bit 0