CD2401 Intel, CD2401 Datasheet - Page 129

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

8.5.2.3
Datasheet
Register Name: RISR
Register Description: Receive Interrupt Status
Default Value: x’00
Access: Word Read only
Register Name: RISRl
Register Description: Receive Interrupt Status - low
Default Value: x’00
Access: Byte Read only
Bit 7
15
7
0
Receive Interrupt Status Register (RISR)
This register reports the status of the channel during the receive interrupt service. It is a 16-bit
register, with the lower byte displaying current receive character oriented status while the upper
byte displays current DMA interrupt status. The upper byte is not used if DMA mode is not active.
HDLC Mode
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 6
EOF
14
6
Reserved – always returns ‘0’ when read
End of Frame
This bit indicates that a valid end of frame was received, and the frame is essentially
complete.
Receive Abort
This bit indicates that an abort sequence terminating the frame was received.
Receive CRC error
This bit indicates that a frame with a valid end of frame was received, but the FCS
was not correct.
Overrun Error
This bit indicates that new data has arrived, but the CD2401 FIFO or Holding regis-
ters are full. The new data is lost, and the overrun indication is flagged on the last
character received before the overrun occurred. In HDLC and Bisync modes, the
remainder of a frame following an overrun is discarded.
Residual Indication
This bit indicates that the last character of the frame was a partial character.
Reserved – always returns ‘0’ when read
Clear Detect
This bit indicates an X.21 data transfer phase clear signal has been detected. This is
RxAbt
Bit 5
13
5
CRC
Bit 4
12
4
Multi-Protocol Communications Controller — CD2401
RISR high
RISR low
Bit 3
OE
11
3
Reslnd
Bit 2
10
2
Motorola Hex Address: x’89
Motorola Hex Address: x’88
Bit 1
Intel Hex Address: x’8A
Intel Hex Address: x’8A
0
9
1
ClrDct
Bit 0
8
0
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