CD2401 Intel, CD2401 Datasheet - Page 41

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

5.2.4
5.2.4.1
Datasheet
Interrupt Cause
Receive Good Data
BREAK detect
Framing error
Parity error
Receive timeout, no data
Special character match
Transmitter empty
Tx FIFO threshold
Receive overrun
Clear detect
CRC error
Residual bit count
Receive abort
End of frame
Transmit underrun
Bus error
End of buffer
Table 2. Transmit and Receive Interrupt Service Requests
Hardware Signals and IACK Cycles
The IACK bus cycle begins with IACKIN* and DS* asserted, and a value matching the appropriate
PILR contents on the least-significant seven address bus bits (A[6:0]). If the IACK cycle is valid
(that is, the PILR values match), the corresponding vector from the interrupting channel LIVR is
driven onto the data bus and DTACK* is asserted. DTACK* is released after DS* is removed.
Figure 4 on page 39
read cycle except that IACKIN* is active, and CS* is inactive.
The three IREQn* pins are open-drain outputs requiring external pull-up resistors, nominally
4.7 k¾. The IACKOUT* is used to form a daisy-chain in systems with more than one CD2401 (see
Section
Programming the PILRs
The three Proirity Interrupt Level registers must be programmed with values that correspond to the
least-significant seven address bits present on A[6:0] during the interrupt acknowledge bus cycle.
Some CPUs output the priority level of the interrupts that are being acknowledged on the bus
during the IACK cycle. In these systems the three PILR values are unique. In other systems that do
not use this scheme, the PILR values can be the same or different depending on the specific design.
When all of the PILRs contain the same value and multiple IREQn* lines are asserted, the CD2401
imposes the following priority scheme to determine which interrupt request is acknowledged:
5.2.5).
Async
shows the interrupt acknowledge cycle timing. It is similar to the basic host
HDLC
Multi-Protocol Communications Controller — CD2401
Bisync
X.21
Not in DMA mode
Not in DMA mode
DMA mode only
DMA mode only
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