CD2401 Intel, CD2401 Datasheet - Page 51

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

5.4.7
Datasheet
Receive DMA Transfer
In all protocol modes, two host memory buffers can be made available to each receive channel, by
the A/BRBADR and A/BRBCNT registers. To make a buffer available, the user must supply the
buffer address in the A/BRBADR registers; the number of free bytes in the buffer must be written
in the A/BRBCNT registers, and the buffer status must be updated in the A/BRBSTS register. The
CD2401 is now free to use the buffer for receive data, and update the appropriate Buffer Status
register. When the buffer is no longer in use, the CD2401 writes the number of bytes stored in the
buffer in RBCNT and updates status in RBSTS. This frees the host to take control of this buffer and
supply a new buffer in its place. The CD2401 automatically switches to the other buffer whenever
one buffer becomes full or the end of a frame has been reached. If the other buffer has not been
allocated, the host still has the time required to fill the CD2401 16-byte FIFO to respond and avoid
loss of data.
Special actions are taken depending on the channel protocol. In HDLC mode, the end-of-frame/
data block boundaries are recognized by the CD2401. When a data-block boundary is detected, the
current buffer is automatically terminated. If the other buffer is allocated and owned by the
CD2401, it becomes the current buffer. End-of-frame and block interrupts are also generated to the
host.
In Asynchronous mode, a host interrupt is generated when there are receive exceptions (framing
error, special character, and so on), but the buffer is not terminated. The data and exception status
are made available to the host, just as when the Asynchronous mode is purely interrupt-driven.
New data is buffered internally in the FIFO until the host services the exception interrupt. The host
has the following three options when terminating an exception interrupt:
These selections are communicated to the CD2401 by the value written by the host to the REOIR,
when the Receive interrupt service is complete. Leaving an ‘n’-byte gap enables the host to insert
status of its own in the current buffer, while continuing to receive data in the same buffer. This
eliminates the overhead of allocating a new buffer. The host must have noted the starting location
of the gap while in the exception interrupt. This is done by reading the RCBADR. The address in
this register is guaranteed to be stable during the Receive interrupt, and to point to the next free
character location in the current DMA buffer. If the size of the gap supplied by the host is sufficient
to fill or complete the current buffer, the CD2401 automatically switches to the other buffer and
advances the RCBADR enough to complete the desired gap. The CD2401 readjusts data alignment
in its internal FIFO as needed to maintain alignment with the external buffer.
Receiver A and B Buffers
In
(DMABSTS, A/BRBADR, A/BRBCNT, A/BRBSTS, and RCBADR) are inside the CD2401.
15. When the CD2401 completes transmission, any necessary CRCs and ending frame delimiters
16. The CD2401 optionally interrupts the host with EOF and EOB set (TISR[6:5]) to indicate that
1. The exception character can be discarded.
2. The buffer can be terminated (if it is, no additional interrupt would be generated). The transfer
3. A user-defined gap can be left in the buffer.
Figure
are transmitted.
the transmission is complete, and this is the last link in the chain.
count is not provided in A/BRBCNT, but can be calculated by RCBADR.
8, buffers A and B are contained in RAM external to the CD2401. All others
Multi-Protocol Communications Controller — CD2401
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