CD2401 Intel, CD2401 Datasheet - Page 143

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

8.6.4
8.6.4.1
Datasheet
Register Name: ARBADRL
Register Description: Receive Buffer ‘A’ 32-bit Address – lower word
Default Value: x’0000
Access: Word Read/Write
Bit 15
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DMA Receive Registers
A Receive Buffer Address – Lower (ARBADRL) Register
Bit 14
Bit 6
Reset Append
This bit is set after the terminate append buffer command in STCR is recognized.
This bit is cleared after the remaining data is flushed from the buffer.
Current Transmit Buffer
This bit is used internally to mark the actual buffer in use.
Append (only buffer A can be used as an append buffer)
This bit is the transmit append buffer usage indicator.
0 = Append buffer is not in use.
1 = Append buffer is in use.
Next Transmit Buffer
0 = buffer A is the next transmit buffer.
1 = buffer B is the next transmit buffer.
This bit is toggled when transmission is started from a buffer (that is, when data is
first read from buffer A). This bit is set to indicate that buffer B is next.
Current Transmit Buffer Busy
0 = no buffer in use.
1 = current transmit buffer in use.
Next Receive Buffer
0 = buffer A is the next receive buffer.
1 = buffer B is the next receive buffer.
This bit is toggled when receive data is first written to a buffer (that is, when data is
first written to buffer A). This bit is set to indicate buffer B is next.
Current Receive Buffer Busy
0 = no buffer in use.
1 = current receive buffer in use.
Bit 13
Bit 5
Binary Address Value, 32-bit Address bits 15:8
Binary Address Value, 32-bit Address bits 7:0
Bit 12
Bit 4
Multi-Protocol Communications Controller — CD2401
Bit 11
Bit 3
Bit 10
Bit 2
Motorola Hex Address: x’42
Bit 9
Bit 1
Intel Hex Address: x’40
Bit 8
Bit 0
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