CD2401 Intel, CD2401 Datasheet - Page 48

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

CD2401 — Multi-Protocol Communications Controller
5.4.5
48
†. A/B is used as a Buffer register abbreviation indicating A buffer / B buffer followed by the register acronym.
Transmit DMA Transfer
As in receive data transfers, two buffers are available for DMA transmit transfers. The A/
BTBADR
These registers are set by the host when initiating a transfer. The CD2401 makes a copy of the
registers to perform the transfer, leaving the originals unchanged. Transfer of buffers between the
host and the CD2401 is controlled by the A/BTBSTS registers.
Buffers can contain either complete frames or blocks of data, linked together to form a complete
frame or a block, or used in an Append mode to transmit data as it arrives from another process.
The first two transfer types are Block mode transfers, the last is the Append mode. Both are further
described below. The management of the buffers reduces the processor overhead associated with
short data transfers and increases the minimum response time requirements for frame-based
transmissions.
Chain Mode Transfer
In Chain mode, the frame should be complete in buffers in memory before transmission is started.
The Append Status bit should not be set; the Start of Frame bit must be set to begin transmission,
and the Last Buffer bit must be set if this buffer is the last in a chained block or is a complete frame
or block.
When the CRC bit is set, the CD2401 generates and transmits a cyclic redundancy check word for
the frame using the polynomial selected by the CPSR. If the Interrupt Required bit is set, a host
interrupt is generated after the buffer is transmitted.
Transmit buffers can be chained to support large frames. To minimize bus usage, the first buffer of
the chain should begin on an even address in host memory. The CD2401 begins fetching a frame
from a buffer performing DMA transfer, reading two bytes at a time. The CD2401 cannot realign
data between external memory and the FIFO. If one buffer of the chain ends on an odd address, the
next buffer in the chain should begin on an odd address. Otherwise, only single-byte transfers are
made for the rest of the buffer.
Append Mode Transfer (Buffer A only)
Append mode transfers are available for buffer A in Asynchronous mode only. If buffer A is set to
Append mode, the host can enable the CD2401 to transmit data in the buffer before it is completely
filled. The CD2401 starts transmitting new data when it is appended to the buffer.
This mode is useful for terminal echo routines that do not wait for a complete block to be formed
before starting transmission. In this mode, transmission is started when the buffer is made available
to the CD2401 by the host; ATBADR and ATBCNT are initialized. Subsequent triggering of DMA
transfer occurs by programming ATBCNT with the accumulated byte count. In this case, ATBCNT
should be written as a 16-bit word to avoid confusion between 2-byte operations. ATBADR should
not be reprogrammed during Append mode. If the memory space has to be moved, the Append
mode must first be disabled. When the final data is added to the append buffer and ATBCNT has
been updated, the host should set the AppdCmp bit (STCR[5]). When the CD2401 has completed
the final transmission, it clears the 2401own bit (ATBSTS[0]), and generates an end-of-buffer
interrupt.
†
and A/BTBCNT registers contain the start address of and the byte count in the buffers.
Datasheet