CD2401 Intel, CD2401 Datasheet - Page 140

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

CD2401 — Multi-Protocol Communications Controller
8.5.4.3
140
Register Name: MISR
Register Description: Modem Interrupt Status
Default Value: x’00
Access: Byte Read/Write
DSRChg
Bit 7
Bit 4
Bits 3:2
Bits 1:0
Modem (/Timer) Interrupt Status Register (MISR)
When the host receives a modem interrupt, the following status is provided in this register.
Bit 7
Bit 6
Bit 5
Bit 4:2
Bit 1
Bit 0
CDChg
Bit 6
Unused – always returns ‘0’ when read.
Modem Vector [1:0]
These bits are set by the CD2401 to provide the least-significant two bits of the vec-
tor supplied to the host CPU during an interrupt acknowledge cycle. Modem vector
is decoded as follows: Mvct [1] = 0, and Mvct [0] = 1.
Modem Channel Number [1:0]
These bits are set by the CD2401 to indicate the channel requiring modem interrupt
service.
DSR Changed
1 = a change is detected on the DSR* input. The change detect is programmed in
COR4 and COR5.
CD Changed
1 = a change is detected on the CD* input. The change detect is programmed in
COR4 and COR5.
CTS Changed
1 = a change is detected on the CTS* input. The change detect is programmed in
COR4 and COR5.
Reserved – always returns ‘0’ when read.
General Timer 2 timed out
The count reached zero before being reset or disabled.
General Timer 1 timed out
The count reached zero before being reset or disabled.
CTSChg
Bit 5
Men
0
1
1
0
0
Mact
Bit 4
0
0
1
1
0
0
Meo
0
0
0
0
1
Bit 3
0
Idle
Modem interrupt requested, but not asserted.
Modem interrupt is asserted.
Modem interrupt is acknowledged.
Modem interrupt service routine is complete.
Bit 2
0
Sequence of Events
Motorola Hex Address: x’8B
Timer2
Bit 1
Intel Hex Address: x’88
Datasheet
Timer1
Bit 0