CD2401 Intel, CD2401 Datasheet - Page 9

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

1.0
Datasheet
Features
HDLC/SDLC (Non-Multidrop) Features
Asynchronous Features
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Four full-duplex multi-protocol channels, each running up to 134.4 kbits/sec. (@ CLK 35
MHz)
Supports async, HDLC/SDLC (synchronous data link control; non-multidrop applications),
bisync and X.21 on all channels
32-bit address, 16-bit data, double-buffered DMA controller for each transmitter and receiver;
two independent bit-rate generators per channel for transmit and receive
On-chip NRZ (nonreturn-to-zero), NRZI (nonreturn-to-zero inverted), and Manchester data
encoding and decoding
DPLL (digital phase-locked loop) on each receiver
Two independent timers per channel
Four 8-bit or two 16-bit frame address matching
FCS generation and validation
CRC (cyclic redundancy check) optionally readable
Programmable leading-pad character transmission
Supports shared flags on receive frames
Programmable number of leading flags
User-programmable and automatic flow control modes
5- to 8-bit character plus optional parity
Enhanced features for UNIX environment
Programmable timer closely coupled with character reception, especially for asynchronous
receive DMA operation
— In-band (software) by XON/XOFF
— Out-of-band (hardware flow control) by RTS/CTS and DTR/DSR
— Line-break detection and generation
— Special-character and character-range recognition and transmission
— Transmit delay
— Character expansion in transmit (for example, sending <LF> will be expanded to <CR>
— Programmable translation of receiving character with error to different pattern (for
— Flow-control transparency and LNext
<LF> automatically)
example, character with parity error can be translated into FFh, 00h character on the
system side)
Multi-Protocol Communications Controller — CD2401
9