CD2401 Intel, CD2401 Datasheet - Page 138

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

CD2401 — Multi-Protocol Communications Controller
8.5.3.6
138
Register Name: TEOIR
Register Description: Transmit End of Interrupt
Default Value: x’00
Access: Byte Write only
TermBuff
Bit 7
Note: If current interrupt is a transmit end-of-buffer interrupt, setting this bit at the end of the service
Transmit End of Interrupt Register (TEOIR)
This register must be written to by the host transmit interrupt service routine to signal to the
CD2401 that the current interrupt service is concluded. This must be the last access to the CD2401
during an interrupt service routine. A write to this register generates an internal end-of-interrupt
signal that pops the CD2401 interrupt context stack.
Depending on the circumstances of an individual interrupt service, the host may be required to pass
a parameter to the CD2401 through these registers. The CD2401 interprets the values written to
this register at the completion of all receive interrupts as commands to be executed.
Bit 7
routine causes the next buffer to also be terminated.
Bit 6
Bit 5
Bit 4
Bit 3
Bits 2:0
Bit 6
EOF
Terminate Buffer
1 = terminates buffer in DMA mode forces the current buffer to be discarded.
End of Frame (Synchronous modes)
This bit uses an interrupt-driven data transfer.
0 = this data transfer does not complete the frame/block.
1 = this data transfer completes the frame/block.
Set General Timer 2 (Synchronous modes)
0 = do not set General Timer 2.
1 = load the value provided in TISR to General Timer 2.
Set General Timer 1 (Synchronous modes)
0 = do not set General Timer 1.
1 = load the value provided in TISR to the high byte of General Timer 1.
At the end of an interrupt service routine, the user can set a timer by setting a timer
value in TISR. When the timer reaches zero, the CD2401 generates a modem/timer
group interrupt to the host.
No Transfer of data
If no data is transferred to the transmit FIFO during a data transfer interrupt, this bit
must be set by the host.
Reserved – must be zero.
SetTm2
Bit 5
SetTm1
Bit 4
Notrans
Bit 3
Bit 2
0
Motorola Hex Address: x’85
Bit 1
Intel Hex Address: x’86
0
Datasheet
Bit 0
0