CD2401 Intel, CD2401 Datasheet - Page 132

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

CD2401 — Multi-Protocol Communications Controller
8.5.2.4
132
Register Name: RISRh
Register Description: Receive Interrupt Status - high
Default Value: x’00
Access: Byte Read only
Bit 7
Berr
Note: This register is used in DMA mode only.
Bits 6:4
Bit 3
Bit 2
Bit 1
Bit 0
During an interrupt service routine, the host can use this register to provide a timer value as
detailed in the REOIR.
Receive Interrupt Status Register high (RISRh)
Bit 7
Bit 6
EOF
Special Character Detect [2:0]
This indication occurs if two consecutive characters matching the value indicated in
the table below are received.
Overrun Error
This bit indicates that the receiver buffer and FIFO were overrun. At least one new
character was received, but lost since there was no room available in the receiver
buffer and/or FIFO. This status is set on the last character received before the over-
run occurred.
Parity Error
This bit indicates that a parity error occurred on this character.
Reserved – always returns ‘0’ when read.
Lead Change
This bit indicates a change of state on the CTS* pin from the previous character time.
Because there is no character sync during some phases of the X.21 call setup, an
Lead Change indication can precede a special character interrupt.
Bus Error (written by CD2401)
0 = no bus error.
1 = bus error detected on last transfer. The actual address at which the error occurred
Bit 5
EOB
SCdet2
0
0
0
0
1
1
1
1
Bit 4
0
SCdet1
0
0
1
1
0
0
1
1
BA/BB
Bit 3
SCdet0
0
1
0
1
0
1
0
1
Bit 2
0
None detected.
Matched the value in SCHR1.
Matched the value in SCHR2.
Matched the value in SCHR3.
All ‘0’ condition.
All ‘1’ condition.
Alternating ‘0’ and ‘1’ condition.
SYN detect.
Motorola Hex Address: x’88
Bit 1
Intel Hex Address: x’8B
0
Status
Datasheet
Bit 0
0