CD2401 Intel, CD2401 Datasheet - Page 6

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

CD2401 — Multi-Protocol Communications Controller
10.0
11.0
Index
Bit Index
Figures
Tables
6
Package Specifications
Ordering Information Example
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24
1
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....................................................................................................................................... 169
....................................................................................................................................... 173
Functional Block Diagram ................................................................................... 11
Host Read Cycle ................................................................................................. 36
Host Write Cycle ................................................................................................. 37
Interrupt Acknowledge Cycle .............................................................................. 39
Bus Acquisition Cycle.......................................................................................... 46
Data Transfer Timing .......................................................................................... 46
Transmitter A and B Buffers................................................................................ 49
Receiver A and B Buffers.................................................................................... 52
DMA Transmit Buffer Selection........................................................................... 55
BRG and DPLL ................................................................................................... 60
Data Encoding..................................................................................................... 64
Transmit Data With External Clock In ................................................................. 64
Transmit Data With External Clock Out .............................................................. 64
DMA Connections for the CD2401...................................................................... 66
CD2401 Async Receive Character Processing................................................... 76
Initialization Sequence for the CD2401............................................................... 88
CLK/BUSCLK/RESET* Timing Relationship..................................................... 159
Slave Read Cycle Timing.................................................................................. 160
Slave Write Cycle Timing .................................................................................. 161
Interrupt Acknowledge Cycle Timing................................................................. 162
Bus Arbitration Cycle Timing............................................................................. 163
Bus Release Timing .......................................................................................... 164
DMA Read Cycle Timing................................................................................... 165
DMA Write Cycle Timing ................................................................................... 166
Pin Descriptions .................................................................................................. 17
Transmit and Receive Interrupt Service Requests.............................................. 41
A and B Buffers and Chaining............................................................................. 47
Clock Source Select............................................................................................ 60
Bit Rate Constants, CLK = 20 MHz..................................................................... 61
Bit Rate Constants, CLK = 25 MHz..................................................................... 61
Bit Rate Constants, CLK = 30 MHz..................................................................... 62
Bit Rate Constants, CLK = 35 MHz..................................................................... 62
Data Clock Selection Using External Clock @ 35 MHz ...................................... 65
DTE Connections ................................................................................................ 67
DCE Connections................................................................................................ 67
Recommended Signal Connection...................................................................... 72
BREAK Sequencing ............................................................................................ 73
....................................................................................... 167
......................................................................... 168
Datasheet