CD2401 Intel, CD2401 Datasheet - Page 19

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

Datasheet
TXCOUT/DTR*
RXCOUT[0–3]
RXCIN[0–3]
TXCIN[0–3]
DSR*[0–3]
RTS*[0–3]
CTS*[0–3]
Table 1. Pin Descriptions (Sheet 3 of 4)
RXD[0–3]
TXD[0–3]
CD*[0–3]
Symbol
TEST
[0–3]
85, 11, 18, 22
56, 60, 65,
55, 59, 64,
25, 32, 37,
54, 58, 63,
44, 48, 50,
43, 46, 49,
53, 57, 61,
39, 40, 41,
34, 35, 36,
Number
Pin
33
69
68
47
67
52
51
66
42
38
Type
O
O
O
O
I
I
I
I
I
I
I
TEST: In normal operation, this pin should be kept low. For board-level testing
purposes, it provides a mechanism for forcing normal output pins to High-
Impedance mode. When the TEST pin is high, the following pins are in High-
Impedance mode: BUSCLK, BGOUT*, IACKOUT*, RXCOUT[0–1], RTS*[1:0],
DTR*[1:0], and TXD[1:0].
To ensure all CD2401 outputs are high-impedance, either of the following two
conditions must be met:
REQUEST TO SEND* [0–3]: This output can be controlled automatically by the
CD2401 to indicate that data is being sent on the TXD pin.
TRANSMIT CLOCK OUT/DATA TERMINAL READY* [0–3]: This output can be
controlled automatically by the CD2401 to indicate a programmable threshold
has been reached in the receive FIFO. It can also be programmed to output the
transmit data clock. Following reset, this pin is high and stays high in Clock
mode until the transmit channel is enabled for the first time; after which it
remains active, independent of the state of the transmit enable. In all modes,
the clock transitions every bit time, even during idle fill in Asynchronous mode.
Data transitions are made on the negative-going edge of TXCOUT.
RECEIVE CLOCK OUT [0–3]: This output provides a one-time bit rate clock for
the receive data in all modes, except when an input (RXCIN) one-time receive
clock is used. After reset, this pin is low until the channel is receive enabled for
the first time, after which it remains active, independent of the state of receive
enable. When in Asynchronous mode, the output only transitions while receiving
data and not during inter-character fill. The receive data is sampled on the
positive-going edge of this clock.
CLEAR TO SEND* [0–3]: This input can be programmed to control the flow of
transmit data, for out-of-band flow control applications.
CARRIER DETECT* [0–3]: This pin is always visible in the MSVR. The CD*
input can be programmed to validate receive data.
TRANSMIT CLOCK [0–3]: This pin inputs the transmit clock to the BRG.
RECEIVE CLOCK [0–3]: This pin inputs the receive clock to the BRG.
DATA SET READY* [0–3]: This pin is always visible in the MSVR. The DSR
input can be programmed to validate receive data.
TRANSMIT DATA [0–3]: Serial data output for each channel.
RECEIVE DATA [0–3]: Serial data input for each channel.
• the RESET* pin can be driven low, and the TEST pin driven high or,
• the CD2401 is kept in the bus idle state (not accessed for read/write
operations nor DMA active), and the TEST pin is driven high.
Multi-Protocol Communications Controller — CD2401
Description
19