CD2401 Intel, CD2401 Datasheet - Page 126

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

CD2401 — Multi-Protocol Communications Controller
8.5.1.3
8.5.1.4
126
Register Name: LICR
Register Description: Local Interrupting Channel
Default Value: C1:C0 contain the channel number
Access: Byte Read/Write
Register Name: STK
Register Description: Interrupt Stack
Default Value: x’00
Access: Byte Read only
CLvl [1]
Bit 7
Bit 7
X
Bit 0
Local Interrupting Channel Register (LICR)
These Per-Channel registers are initialized with each channel number. The locations are RAM
registers and can be used for any purpose.
Bits 7:4
Bits 3:2
Bits 1:0
Interrupt Stack Register (STK)
This register is a four-deep-by-two-bit-wide stack that contains the internal interrupt nesting
history. The stack is pushed from bits 7 and 0 toward the center during an interrupt acknowledge
cycle, and popped from the center during a write to an end of interrupt register.
CLvl[1:0]
MLvl [1]
Bit 6
Bit 6
X
Transmit Data
Any transmit exception or transmit FIFO threshold reached in Interrupt Transfer
mode. Group 2 interrupts are generated at the end of transmit DMA buffers or when
the FIFO threshold is reached in Interrupt Transfer mode.
User-defined
Channel nuber [1:0]
These bits define the interrupting channel number.
User-defined
These bits provide the currently active interrupt level.
TLvl [1]
Bit 5
Bit 5
X
C1
0
0
1
1
Bit 4
Bit 4
0
X
C0
0
1
0
1
Bit 3
Bit 3
C1
0
TLvl [0]
Channel Number
Bit 2
Bit 2
C0
Channel 0
Channel 1
Channel 2
Channel 3
Motorola Hex Address: x’E2
Motorola Hex Address: x’26
MLvl [0]
Bit 1
Bit 1
Intel Hex Address: x’E0
X
Intel Hex Address: x’25
Datasheet
CLvl [0]
Bit 0
Bit 0
X