CD2401 Intel, CD2401 Datasheet - Page 128

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

CD2401 — Multi-Protocol Communications Controller
8.5.2.2
128
Register Name: RIR
Register Description: Receive Interrupt Register
Default Value: x’00
Access: Byte Read only
Bit 7
Ren
Receive Interrupt Register (RIR)
Bit 7
Bit 6
Bit 5
Bit 4
Bits 3:2
Bits 1:0
Bit 6
Ract
Receive Enable
This bit is set by the CD2401 to initiate a receive interrupt request sequence. This bit
is cleared during a valid receive interrupt acknowledge cycle.
Receive Active
This bit is set automatically when Ren is set, and the Fair Share logic allows the
assertion of a receive interrupt request. This bit is cleared when the host CPU writes
to the REIOR.
Receive End of Interrupt
This bit is automatically set when the host CPU writes to the REIOR during a receive
interrupt routine.
Unused – always returns ‘0’ when read.
Receive Vector [1:0]
These bits are set by the CD2401 to provide the lower 2 bits of the vector supplied
to the host CPU during an interrupt acknowledge cycle.
The Receive Good Data vector is decoded as: Rvct [1] = 1, Rvct [0] = 1
The Receive exception vector is decoded as: Rvct [1] = 0, Rvct [0] = 0
Receive Channel Number [1:0]
These bits are set by the CD2401 to indicate the channel requiring receive interrupt
service.
Bit 5
Reoi
Ren
0
1
1
0
0
Bit 4
0
Ract
0
0
1
1
0
Rvct [1]
Bit 3
Reoi
0
0
0
0
1
Idle
Receive interrupt requested, but not
asserted.
Receive interrupt is asserted.
Receive interrupt is acknowledged.
Receive interrupt service routine is
complete.
Rvct [0]
Bit 2
Sequence of Events
Motorola Hex Address: x’ED
Rcn [1]
Bit 1
Intel Hex Address: x’EF
Datasheet
Rcn [0]
Bit 0